Strain-Gated Piezotronic Transistors Based on Vertical Zinc Oxide

TLDR: In this article, a strain-gated piezotronic transistors were fabricated using vertically aligned ZnO nanowires (NWs), which were grown on GaN/sapphire substrates using a vapor-liquidsolid process.

Abstract: Strain-gated piezotronic transistors have been fabricated using vertically aligned ZnO nanowires (NWs), which were grownon GaN/sapphire substrates using a vaporliquidsolid process. The gate electrode of the transistor is replaced by the internal crystal potential generated by strain, and the control over the transported current is at the interface between the nanowire and the top or bottom electrode. The currentvoltage characteristics of the devices were studied using conductive atomic force microscopy, and the results show that the current flowing through the ZnO NWs can be tuned/gated by the mechanical force applied to the NWs. This phenomenon was attributed to the piezoelectric tuning of the Schottky barrier at the AuZnO junction, known as the piezotronic effect. Our study demonstrates the possibility of using Au droplet capped ZnO NWs as a transistor array for mapping local strain. More importantly, our design gives the possibility of fabricating an array of transistors using individual vertical nanowires that can be controlled independently by applying mechanical force/pressure over the top. Such a structure is likely to have important applications in high- resolution mapping of strain/force/pressure.