Stress‐related problems in silicon technology

TLDR: In this paper, the authors review the achievements to date in understanding and modeling diverse stress problems in silicon integrated circuits, including CVD (chemical vapor deposition) silicon nitride, silicon dioxide, polycrystalline silicon, etc.

Abstract: The silicon integrated‐circuits chip is built by contiguously embedding, butting, and overlaying structural elements of a large variety of materials of different elastic and thermal properties. Stress develops in the thermal cycling of the chip. Furthermore, many structural elements such as CVD (chemical vapor deposition) silicon nitride, silicon dioxide, polycrystalline silicon, etc., by virtue of their formation processes, exhibit intrinsic stresses. Large localized stresses are induced in the silicon substrate near the edges and corners of such structural elements. Oxidation of nonplanar silicon surfaces produces another kind of stress that can be very damaging, especially at low oxidation temperatures. Mismatch of atomic sizes between dopants and the silicon, and heteroepitaxy produce another class of strain that can lead to the formation of misfit dislocations. Here we review the achievements to date in understanding and modeling these diverse stress problems.