Journal ArticleDOI
Threshold Voltage Instabilities of Present SiC-Power MOSFETs under Positive Bias Temperature Stress
TLDR
In this article, the threshold voltage instability of commercially available silicon carbide (SiC) power MOSFETs or prototypes from four different manufacturers under positive bias temperature stress (PBTS) was studied.Abstract:
We study the threshold voltage (Vth) instability of commercially available silicon carbide (SiC) power MOSFETs or prototypes from four different manufacturers under positive bias temperature stress (PBTS). A positive bias near the Vth causes a threshold voltage shift of 0.7 mV per decade in time per nanometer oxide thickness in the temperature range between-50 °C and 150 °C. Recovery at +5 V after a 100 s +25 V gate-pulse causes a recovery between-1.5 mV/dec/nm and-1.0 mV/dec/nm at room temperature and is decreasing with temperature. All devices show similar stress, recovery and temperature dependent behavior indicating that the observed Vth instabilities are likely a fundamental physical property of the SiC-SiO2 system caused by electron trapping in near interface traps. It is important to note that the trapping is not causing permanent damage to the interface like H-bond-breakage in silicon based devices and is nearly fully reversible via a negative gate bias.read more
Citations
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Journal ArticleDOI
Understanding BTI in SiC MOSFETs and Its Impact on Circuit Operation
TL;DR: In this paper, the authors investigated the capture and emission time constants of positive and negative charge trapped in the gate oxide and at the interface of SiC power MOSFETs as a function of gate bias.
Proceedings ArticleDOI
Understanding and modeling transient threshold voltage instabilities in SiC MOSFETs
TL;DR: This work investigates the capture- and emission-time constants of positive and negative charge trapped in the gate oxide and at the interface as a function of gate bias and temperature and presents a very accurate model for the short-term hysteresis during a bipolar AC period.
Proceedings ArticleDOI
Threshold voltage hysteresis in SiC MOSFETs and its impact on circuit operation
TL;DR: In this article, the capture and emission-time constants of positive and negative charge trapped in the gate oxide and interface as a function of gate bias were investigated and it was shown that threshold voltage hysteresis has no harmful effect on switching operation.
Journal ArticleDOI
Electrically detected magnetic resonance of carbon dangling bonds at the Si-face 4H-SiC/SiO2 interface
Gernot Gruber,Jonathon Cottom,Robert Meszaros,Markus Koch,Gregor Pobegen,Thomas Aichinger,Dethard Peters,Peter Hadley +7 more
TL;DR: In this article, the dominant hyperfine (HF) spectra measured of different SiC MOSFETs are compared, and it is argued that the same dominant defect is present in all devices.
Proceedings ArticleDOI
Gate-oxide reliability and failure-rate reduction of industrial SiC MOSFETs
Thomas Aichinger,M. Schmidt +1 more
TL;DR: The results of this test demonstrate that excellent gate-oxide reliability of commercially available SiC trench MOSFETs can be achieved after applying a sufficiently precise electrical screening.
References
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Journal ArticleDOI
Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements
Aivars J. Lelis,Daniel B. Habersat,Ronald Green,Aderinto Ogunniyi,M. Gurfinkel,J. Suehle,Neil Goldsman +6 more
TL;DR: In this article, the authors observed significant instability in the threshold voltage of 4H-SiC metal-oxide-semiconductor field effect transistors due to gate-bias stressing.
Journal ArticleDOI
High channel mobility in inversion layers of 4H-SiC MOSFETs by utilizing (112~0) face
TL;DR: In this article, an improvement of channel mobility in 4H-SiC MOSFETs was achieved by utilizing the (112~0) face: 17 times higher channel mobility than that on the conventional (0001) Si-face (5.59 cm/sup 2//Vs).
Journal ArticleDOI
Bias-stress induced threshold voltage and drain current instability in 4H–SiC DMOSFETs
TL;DR: In this paper, the instability of n-channel 4H-SiC double-implanted metal-oxide-semiconductor field effect transistors (DMOSFETs) was studied, in terms of thresholdvoltage (V TH ) shifts and drain-source current (I DS ) transients, for different gate bias stress durations of range 100-5500 s.
Journal ArticleDOI
On the temperature dependence of NBTI recovery
TL;DR: The understanding of the recovery physics can be probed in an unprecedented manner by using this technique, which is able to perform NBTI at a certain stress temperature, which generates a certain degradation level, while the recovery itself can be studied at arbitrary temperatures.