Transient program operation model considering distribution of electrons in 3D NAND flash memories
Dong Chan Lee,Hyungcheol Shin +1 more
TLDR
A modified 1-D Poisson equation was proposed that shows better accuracy than the existing model by reflecting the spatial distribution of electrons trapped by the program operation of 3D NAND Flash memories.Abstract:
We developed a new compact model for the program operation of 3D NAND Flash memories. A modified 1-D Poisson equation was proposed that shows better accuracy than the existing model by reflecting the spatial distribution of electrons trapped by the program operation. Under various conditions of program voltage (VPGM) and program time (tPGM), the threshold voltage shift (∆Vt ) was extracted by TCAD (Technology Computer-Aided Design) simulation, and we used this data to validate our new model. It also provides validity of the model for program operation in 3D NAND flash memory along with various TCAD analysis data.read more
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Journal ArticleDOI
Fowler‐Nordheim Tunneling into Thermally Grown SiO2
M. Lenzlinger,E. H. Snow +1 more
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Jae-Hoon Jang,Han-soo Kim,Wonseok Cho,Hoosung Cho,Jinho Kim,Sun Il Shim,Younggoan Jang,Jae-Hun Jeong,Byoungkeun Son,Dongwoo Kim,Kihyun,Jae-Joo Shim,Jin Soo Lim,Kyoung-hoon Kim,Su Youn Yi,Ju-Young Lim,De-will Chung,Hui-chang Moon,Sung-Min Hwang,Jong-Wook Lee,Yong-Hoon Son,U-In Chung,Won-Seong Lee +22 more
TL;DR: Damascened metal gate SONOS type cell in the vertical NAND flash string is realized by a unique dasiagate replacementpsila process and conventional bulk erase operation of the cell is successfully demonstrated.
Journal ArticleDOI
A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme
Kang-Deog Suh,Byung-Hoon Suh,Young-Ho Lim,Jin-Ki Kim,Young-joon Choi,Yong-Nam Koh,Sung-Soo Lee,Suk-Chon Kwon,Byung-Soon Choi,Jin-Sun Yum,Jung-Hyuk Choi,Jang-Rae Kim,Hyung-Kyu Lim +12 more
TL;DR: A 3.3 V-only 32 Mb NAND flash memory that achieves not only high performance but also low cost with a 94.9 mm/sup 2/ die size, improved yields, and a simple process with 0.5 /spl mu/m CMOS technology is described.