Proceedings ArticleDOI
Trustworthy computing in a multi-core system using distributed scheduling
David R. McIntyre,Francis Wolff,Christos A. Papachristou,Swarup Bhunia +3 more
- pp 211-213
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TLDR
A distributed software scheduling prototype, TADS (Trojan Aware Distributed Scheduling), is presented to achieve a Trojan-activation tolerant trustworthy computing system in a multi-core processor potentially containing hardware Trojans.Abstract:
Hardware Trust is an emerging problem in semiconductor integrated circuit (IC) security due to widespread outsourcing and the stealthy nature of hardware Trojans. Conventional post-manufacturing testing, test generation algorithms and test coverage metrics cannot be readily extended to hardware Trojan detection. As a result there is a need to develop approaches that will ensure trusted in-field operation of ICs, and more generally trust in computing. We present a distributed software scheduling prototype, TADS (Trojan Aware Distributed Scheduling), to achieve a Trojan-activation tolerant trustworthy computing system in a multi-core processor potentially containing hardware Trojans. TADS is designed to be transparent to applications and can run on general purpose multicore PEs without modifications to the operating system or underlying hardware. TADS can, with high confidence, continue to correctly execute its specified queue of job subtasks in the presence of hardware Trojans in the multi-core PEs while learning the individual trustworthiness of the individual PEs. Specially crafted self-checking subtasks called bounty hunters are introduced to accelerate PE trust learning. Also, by learning and maintaining individual PE trustworthiness, the scheduler is able to achieve Trojan containment by scheduling subsequent job subtasks to PEs with high learned trust.read more
Citations
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Journal ArticleDOI
Hardware Trojans: Lessons Learned after One Decade of Research
TL;DR: This article examines the research on hardware Trojans from the last decade and attempts to capture the lessons learned and identifies the most critical lessons for those new to the field and suggests a roadmap for future hardware Trojan research.
Journal ArticleDOI
Design and Validation for FPGA Trust under Hardware Trojan Attacks
Sanchita Mal-Sarkar,Robert Karam,Seetharam Narasimhan,Anandaroop Ghosh,Aswin Krishna,Swarup Bhunia +5 more
TL;DR: This paper presents a taxonomy of FPGA-specific hardware Trojan attacks based on activation and payload characteristics along with Trojan models that can be inserted by an attacker, and proposes a novel design approach, referred to as Adapted Triple Modular Redundancy (ATMR), to reliably protect against Trojan circuits of varying forms in FPGAs.
Journal ArticleDOI
Efficient Control-Flow Subgraph Matching for Detecting Hardware Trojans in RTL Models
TL;DR: A verification approach that detects different types of HTs in RTL models by exploiting an efficient control-flow subgraph matching algorithm and is effective and efficient in comparison with other state-of-the-art solutions.
Journal ArticleDOI
Dynamic Function Verification for System on Chip Security Against Hardware-Based Attacks
Lok-Won Kim,John Villasenor +1 more
TL;DR: The proposed approach provides a comprehensive architectural design method aimed at system on chip (SoC) based hardware systems that performs run-time testing, detects run- time attacks by Trojans, mitigates them, quarantines the detected malicious hardware modules, and regenerates the lost system functions with modest cost.
Journal ArticleDOI
Dynamic Function Replacement for System-on-Chip Security in the Presence of Hardware-Based Attacks
Lok-Won Kim,John Villasenor +1 more
TL;DR: Architectural features of System-on-Chip (SoC) that can minimize performance degradation and maximize the likelihood of seamless system operation despite the function replacement are proposed.
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