scispace - formally typeset
Proceedings ArticleDOI

Trustworthy computing in a multi-core system using distributed scheduling

Reads0
Chats0
TLDR
A distributed software scheduling prototype, TADS (Trojan Aware Distributed Scheduling), is presented to achieve a Trojan-activation tolerant trustworthy computing system in a multi-core processor potentially containing hardware Trojans.
Abstract
Hardware Trust is an emerging problem in semiconductor integrated circuit (IC) security due to widespread outsourcing and the stealthy nature of hardware Trojans. Conventional post-manufacturing testing, test generation algorithms and test coverage metrics cannot be readily extended to hardware Trojan detection. As a result there is a need to develop approaches that will ensure trusted in-field operation of ICs, and more generally trust in computing. We present a distributed software scheduling prototype, TADS (Trojan Aware Distributed Scheduling), to achieve a Trojan-activation tolerant trustworthy computing system in a multi-core processor potentially containing hardware Trojans. TADS is designed to be transparent to applications and can run on general purpose multicore PEs without modifications to the operating system or underlying hardware. TADS can, with high confidence, continue to correctly execute its specified queue of job subtasks in the presence of hardware Trojans in the multi-core PEs while learning the individual trustworthiness of the individual PEs. Specially crafted self-checking subtasks called bounty hunters are introduced to accelerate PE trust learning. Also, by learning and maintaining individual PE trustworthiness, the scheduler is able to achieve Trojan containment by scheduling subsequent job subtasks to PEs with high learned trust.

read more

Citations
More filters
Journal ArticleDOI

Hardware Trojans: Lessons Learned after One Decade of Research

TL;DR: This article examines the research on hardware Trojans from the last decade and attempts to capture the lessons learned and identifies the most critical lessons for those new to the field and suggests a roadmap for future hardware Trojan research.
Journal ArticleDOI

Design and Validation for FPGA Trust under Hardware Trojan Attacks

TL;DR: This paper presents a taxonomy of FPGA-specific hardware Trojan attacks based on activation and payload characteristics along with Trojan models that can be inserted by an attacker, and proposes a novel design approach, referred to as Adapted Triple Modular Redundancy (ATMR), to reliably protect against Trojan circuits of varying forms in FPGAs.
Journal ArticleDOI

Efficient Control-Flow Subgraph Matching for Detecting Hardware Trojans in RTL Models

TL;DR: A verification approach that detects different types of HTs in RTL models by exploiting an efficient control-flow subgraph matching algorithm and is effective and efficient in comparison with other state-of-the-art solutions.
Journal ArticleDOI

Dynamic Function Verification for System on Chip Security Against Hardware-Based Attacks

TL;DR: The proposed approach provides a comprehensive architectural design method aimed at system on chip (SoC) based hardware systems that performs run-time testing, detects run- time attacks by Trojans, mitigates them, quarantines the detected malicious hardware modules, and regenerates the lost system functions with modest cost.
Journal ArticleDOI

Dynamic Function Replacement for System-on-Chip Security in the Presence of Hardware-Based Attacks

TL;DR: Architectural features of System-on-Chip (SoC) that can minimize performance degradation and maximize the likelihood of seamless system operation despite the function replacement are proposed.
References
More filters
Proceedings ArticleDOI

SWIFT: Software Implemented Fault Tolerance

TL;DR: A novel, software-only, transient-fault-detection technique, called SWIFT, which efficiently manages redundancy by reclaiming unused instruction-level resources present during the execution of most programs and provides a high level of protection and performance with an enhanced control-flow checking mechanism.
Book ChapterDOI

MERO: A Statistical Approach for Hardware Trojan Detection

TL;DR: A test pattern generation technique based on multiple excitation of rare logic conditions at internal nodes that maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation.
Journal ArticleDOI

The Hunt For The Kill Switch

TL;DR: The Trust in Integrated Circuits (TIIC) program as discussed by the authors is a three-year initiative to verify the integrity of the military's integrated circuits, including the F-35.
Proceedings ArticleDOI

Towards trojan-free trusted ICs: problem analysis and detection scheme

TL;DR: This work analyzes and formulates the trojan detection problem based on a frequency analysis under rare trigger values and provides procedures to generate input trigger vectors and trojan test vectors to detect trojan effects.
Journal ArticleDOI

A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans Under Real Process and Environmental Conditions

TL;DR: This paper investigates the sensitivity of a power supply transient signal analysis method for detecting Trojans and focuses on determining the smallest detectable Trojan, i.e., the least number of gates a Trojan may have and still be detected, using a set of process simulation models that characterize a TSMC 0.18 μm process.
Related Papers (5)