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This paper proposes new processor architecture to exploit the increasingly number of transistors per integrated circuit and improve the performance of data parallel applications on general-purpose processors.
Moreover, actual processor performance has increased faster than Moore’s law would predict, because processor designers have been able to harness the increasing numbers of transistors available on modern chips to extract more parallelism from software.
The proposed circuit structure and the procedure virtually eliminate usual constraint on the number of transistors that can be present in an array.
Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors.
The fabricated transistors exhibit excellent I-V characteristics.
The operation granularity of the CPU, FE and MX-2 are 32bit, 16bit, and 4bit respectively, and thus we can assign the appropriate processor for each task in an effective manner.
In this regime, utilizing transistors to design specialized cores that optimize energy-per-computation becomes an effective approach to improve system performance.
Proceedings ArticleDOI
Janarbek Matai, Joo-Young Kim, Ryan Kastner 
18 Jun 2014
20 Citations
Additionally, our hardware accelerated implementation is up to 80% faster and over 230 times more energy efficient than a highly optimized Core i7 implementation.
Journal ArticleDOI
C. McNairy, D. Soltis 
01 Mar 2003-IEEE Micro
160 Citations
The Itanium 2 processor extends the processing power of the Itanium processor family with a capable and balanced microarchitecture.
While one might opt to use these transistors for building complex single processor based architectures, recent trends indicate a shift towards on-chip multiprocessor systems since they are simpler to implement and can provide better performance.