Journal ArticleDOI
Design of Sequential Elements for Low Power Clocking System
TLDR
A novel clocked pair shared flip-flop is proposed which reduces the number of local clocked transistors by approximately 40% and a 24% reduction of clock driving power is achieved.Abstract:
Power consumption is a major bottleneck of system performance and is listed as one of the top three challenges in International Technology Roadmap for Semiconductor 2008. In practice, a large portion of the on chip power is consumed by the clock system which is made of the clock distribution network and flop-flops. In this paper, various design techniques for a low power clocking system are surveyed. Among them is an effective way to reduce capacity of the clock load by minimizing number of clocked transistors. To approach this, we propose a novel clocked pair shared flip-flop which reduces the number of local clocked transistors by approximately 40%. A 24% reduction of clock driving power is achieved. In addition, low swing and double edge clocking, can be easily incorporated into the new flip-flop to build clocking systems.read more
Citations
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Journal ArticleDOI
Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme
TL;DR: A novel low-power pulse-triggered flip-flop design is presented that features the best power-delay-product performance in seven FF designs under comparison and a conditional pulse-enhancement technique is devised to speed up the discharge along the critical path only when needed.
Journal ArticleDOI
Power Optimization Techniques for Sequential Elements Using Pulse Triggered Flip-Flops with SVL Logic
TL;DR: This project moves around in replacing conventional master-slave based flip-flop to a pulse triggered flip flop which acts as a tribute alternate for low power applications.
Journal ArticleDOI
Low Power Techniques for Digital System Design
TL;DR: The authors have presented and analyzed some power reduction techniques that can be targeted at different levels of design hierarchy for different target platform and would also discuss concept of ACPI module designed for newer operating systems, which provides basic power management facilities to save system power.
Journal ArticleDOI
Optimization of Web Service-Based Control System for Balance Between Network Traffic and Delay
Chen Hou,Qianchuan Zhao +1 more
TL;DR: The problem of finding the optimal polling frequency control policy of a Web service-based control system as a constrained Markov decision process (CMDP) is formulates and an algorithm called CMDPA is proposed to solve the problem.
Journal ArticleDOI
Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag
TL;DR: A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article, which has features of high performance and low power.
References
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Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.
Patent
Digital integrated circuits
TL;DR: Digital Integrated Circuits addresses today's most significant and compelling industry topics, including: the impact of interconnect, design for low power, issues in timing and clocking, design methodologies, and the tremendous effect of design automation on the digital design perspective.
Book
Design of High-Performance Microprocessor Circuits
TL;DR: The design of next generation microprocessors in deep submicron CMOS technologies is covered, and a broad range of circuit styles and VLSI design techniques are covered, an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers.
Journal ArticleDOI
Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems
TL;DR: A new simulation and optimization approach is presented, targeting both high-performance and power budget issues, and the analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles.
Journal ArticleDOI
Improved sense-amplifier-based flip-flop: design and measurements
Borivoje Nikolic,Vojin G. Oklobdzija,Vladimir Stojanovic,Wenyan Jia,James Kar Shing Chiu,M. Ming-Tak Leung +5 more
TL;DR: The design and experimental evaluation of a new sense-amplifier-based flip-flop (SAFF) is presented and it is found that the main speed bottleneck of existing SAFF's is the cross-coupled set-reset (SR) latch in the output stage.