Showing papers on "Analog-to-digital converter published in 2005"

A time-to-digital-converter-based CMOS smart temperature sensor

Abstract: A time-to-digital-converter-based CMOS smart temperature sensor is proposed for high-accuracy portable applications. Conventional smart temperature sensors rely on an analog-to-digital converter, which consumes much chip area and operating power, for digital output code conversion. For the purpose of cost reduction and power saving, the proposed smart temperature sensor first generates a pulse with a width proportional to the measured temperature. Then, a cyclic time-to-digital converter (TDC) is utilized to convert the pulse into the corresponding digital code. The test chips, with extremely small area of 0.175 mm/sup 2/, were fabricated by the TSMC CMOS 0.35 /spl mu/m 2P4M process. Due to the excellent linearity of the digital output, the achieved measurement error is merely -0.6/spl deg/C to +0.8/spl deg/C without any curvature correction or dynamic offset-cancellation. The effective resolution is better than 0.15/spl deg/C, and the power consumption is 10 /spl mu/W.

Comprehensive digital correction of mismatch errors for a 400-msamples/s 80-dB SFDR time-interleaved analog-to-digital converter

Abstract: Comprehensive digital calibration of a high-speed and high-resolution time-interleaved analog-to-digital converter (TIADC) is described. A channel transfer function, which incorporates all linear errors between analog input and digital output, is measured for each channel by applying a series of sinusoids. A set of finite-impulse response (FIR) filters designed by the weighted least squares principle provides frequency-dependent mismatch correction so that the spurious-free dynamic range (SFDR) is no longer limited by channel mismatches. A four-channel TIADC prototype with 14-bit resolution and 400-MHz aggregate sampling rate was built to verify the proposed correction method. Uncalibrated SFDR was below 50 dB. After mismatch correction with 61-tap FIR filters, 80 dB of SFDR was achieved up to /spl sim/175 MHz of input frequency.

A 106-dB SNR hybrid oversampling analog-to-digital converter for digital audio

Abstract: An audio /spl Sigma//spl Delta/ analog-to-digital converter (ADC) with the loop filter implemented by continuous-time (CT) and discrete-time (DT) circuits is presented. A tuning circuit is used to compensate for changes in the RC product due to process skew, power supply, temperature and sampling rate variation. To eliminate errors caused by inter-symbol interference (ISI) in the CT feedback DAC, a return-to-zero (RTZ) switching scheme is applied on the error current of the CT integrator. The converter is fabricated in a 0.35-/spl mu/m CMOS process, and achieves 106-dB dynamic range, -99-dB THD+N.

A time-based energy-efficient analog-to-digital converter

Abstract: Dual-slope converters use time to perform analog-to-digital conversion but require 2/sup N+1/ clock cycles to achieve N bits of precision. We describe a novel current-mode algorithm that also uses time to perform analog-to-digital conversion but requires 5N clock cycles to achieve N bits of precision via a successive subranging technique. The algorithm requires one asynchronous comparator, two capacitors, one current source, and a state machine. Amplification of two is achieved without the use of an explicit amplifier by simply doing things twice in time. The use of alternating voltage-to-time and time-to-voltage conversions provides natural error cancellation of comparator offset and delay, 1/f noise, and switching charge-injection. The use of few components and an efficient mechanism for amplification and error cancellation allow for energy-efficient operation: in a 0.35-/spl mu/m implementation, we were able to achieve 12 bit of DNL limited precision or 11 bit of thermal noise-limited precision at a sampling frequency of 31.25 kHz with 75 /spl mu/W of total analog and digital power consumption. These numbers yield a thermal noise-limited energy efficiency of 1.17 pJ per quantization level, making it one of the most energy-efficient converters to date in the 10-12 bit precision range.

A 15-b 40-MS/s CMOS pipelined analog-to-digital converter with digital background calibration

Abstract: This study presents a 15-b 40-MS/s switched-capacitor CMOS pipelined analog-to-digital converter (ADC). High resolution is achieved by using a correlation-based background calibration technique that can continuously monitor the transfer characteristics of the critical pipeline stages and correct the digital output codes accordingly. The calibration can correct errors associated with capacitor mismatches and finite opamp gains. The ADC was fabricated using a 0.25-/spl mu/m 1P5M CMOS technology. Operating at a 40-MS/s sampling rate, the ADC attains a maximum signal-to-noise-plus-distortion ratio of 73.5 dB and a maximum spurious-free-dynamic-range of 93.3 dB. The chip occupies an area of 3.8/spl times/3.6 mm/sup 2/, and the power consumption is 370 mW with a single 2.5-V supply.

Read channel apparatus for asynchronous sampling and synchronous equalization

Abstract: A read channel and method using that read channel are disclosed. The read channel comprises an analog to digital converter which asynchronously samples at a fixed rate an analog signal formed by reading a data track, where that data track was written to a data storage medium at a symbol rate and an interpolator interconnected with the analog to digital converter. The read channel further comprises a fractionally-spaced equalizer, where the interpolator provides an interpolated signal to the fractionally-spaced equalizer at an interpolation rate, where that interpolation rate is greater than the symbol rate. The fractionally-spaced equalizer forms a synchronous equalized signal. The read channel further comprises a gain control module interconnected with the fractionally-spaced equalizer, and a sequence detector interconnected with the gain control module.

Ultra-wideband analog-to-digital conversion via signal expansion

Abstract: We consider analog to digital (A/D) conversion, based on the quantization of coefficients obtained via the projection of a continuous time signal over a set of basis functions. The framework presented here for A/D conversion is motivated by the sampling of an input signal in domains which may lead to significantly less demanding A/D conversion characteristics, i.e., lower sampling rates and lower bit resolution requirements. We show that the proposed system efficiently parallelizes the analog to digital converter (ADC), which lowers the sampling rate requirements by increasing the number of basis functions on which the continuous time signal is projected, leading to a tradeoff between sampling rate reduction and system complexity. Additionally, the A/D conversion resolution requirements can be reduced by optimally assigning the available number of bits according to the variance distribution of the coefficients obtained from the signal projection over the new A/D conversion domain. In particular, we study A/D conversion in the frequency domain, where samples of the continuous signal spectrum are taken such that no time aliasing occurs in the discrete time version of the signal. We show that the frequency domain ADC overcomes some of the difficulties encountered in conventional time-domain methods for A/D conversion of signals with very large bandwidths, such as ultra-wideband (UWB) signals. The proposed A/D conversion method is compared with conventional ADCs based on pulse code modulation (PCM). Fundamental figures of merit in A/D conversion and system tradeoffs are discussed for the proposed ADC. The signal-to-noise and distortion ratios of the frequency domain ADC are presented, which quantify the impact of the most critical impairments of the proposed ADC technique. We also consider application to communications receivers, and provide a design example of a multi-carrier UWB receiver.

System and method for adjusting dynamic range of analog-to-digital converter

Abstract: Techniques for adjusting the dynamic range of an A/D converter in response to various conditions are disclosed. A value output by the A/D converter is utilized to determine if the A/D converter is operating at or above its current dynamic range capabilities (i.e., the A/D converter is potentially “saturated” at its current dynamic range setting). If potentially saturated, the dynamic range of the A/D converter may be increased. If not, the dynamic range of the A/D converter may be decreased or may be unchanged. Alternately, an upcoming or enacted change in the gain settings of one or more gain stages that condition the analog signal input to an A/D converter may be used as a condition that results in an adjustment to the dynamic range of the A/D converter.

Continuous-time time-stretched analog-to-digital converter array implemented using virtual time gating

Abstract: We demonstrate the continuous-time operation of a time-stretch analog-to-digital converter array. A continuous-time RF signal is segmented into parallel channels and each channel is stretched in time prior to digitization. The technique offers improvement in the effective input bandwidth and sampling rate of the digitizer. The implementation uses virtual time gating for interleaving segments of the continuous-time RF signal. The signal is first modulated onto a linearly chirped optical carrier and then sliced, in time, using passive optical filters. This technique obviates the need for fast switching gates. It results in minimum interchannel mismatch and in hardware efficiency since all channels are stretched using the same electro-optic modulator and the same dispersive elements.

Phase adjust using relative error

Abstract: A system may adjust the times at which data is sampled by separate sampling mechanisms. Here, it may be desirable to ensure that one sampler samples data at substantially the same time as the other sampler. For example, output data from a high speed sampler that samples received data may be compared with an output of an analog to digital converter that samples the received data at a lower data rate. This difference or relative error may be accumulated over a period of time for given values of delay applied to the clock for the analog to digital converter. In this way, a delay value that minimizes the relative error may be selected as a desired delay value.

RFID reader utilizing an analog to digital converter for data acquisition and power monitoring functions

Abstract: A reader for an RFID system includes an internal power source, a signal generator for generating a detection signal containing analog data and an excitation signal, a transmitting antenna for transmitting the detection and excitation signals, and a receiving antenna for receiving a transponder data signal from a transponder containing digital data. Receiver electronics are coupled with the receiving antenna for conditioning the transponder data signal before reading the digital data. The reader further includes a single-chip microcontroller coupled with the internal power source and the receiver electronics. The single-chip microcontroller has an analog to digital converter to measure the declining power level of the internal power source and to acquire the analog data from the detection signal and the digital data from the transponder data signal. The single-chip microcontroller also includes a firmware and/or software-based demodulator for demodulating the transponder data signal to read the digital data.

System and method for improved time-interleaved analog-to-digital converter arrays

Abstract: System and method for improved time-interleaved analog-to-digital converter arrays which reduces sampling mismatch distortion found in prior art arrays. There may be two causes of non-uniform sampling mismatch in a TI-ADC array, a mismatch due to skew and a mismatch due to clock jitter. To minimize non-uniform sampling mismatch, the mismatch due to skew can be addressed. A preferred embodiment comprises adjusting a delay imparted on the sampling clock by an adjustable delay in each channel of a plurality of channels in the TI-ADC array to minimize skew and randomly switching between two delays that span a zero-skew delay to reduce residual skew in each channel and thus eliminate (or reduce) frequency domain tones caused by non-uniform sampling mismatch.

Format efficient timing acquisition for magnetic recording read channels

Abstract: A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.

Analog-to-digital converter with range error detection

Abstract: A circuit (200) includes a multiplexer (204), an analog-to-digital converter (208), and a processor (216) that compares a sequence (DM) of digital outputs from the analog-to-digital converter to a sequence (217) of normal ranges that correspond with the digital outputs in order to provide an error output (219) when one of the digital outputs is outside its normal range.

Method and apparatus for sensing flash memory using delta sigma modulation

Abstract: A simple method and device for accurately measuring flash memory cell current. The sensing scheme comprises an integrator, an analog to digital converter, and a digital to analog converter. The method comprises the acts of applying an input current and a feedback output current to a summer, integrating the resulting summer output over time, passing the integrated output to a clocked comparator, outputting a comparator output which controls a feedback circuit that keeps the integrator's voltage at the same level as a reference voltage, and outputting a digital average current to a counter. Delta sigma modulation (averaging) is employed to cancel out noise that would otherwise affect the cell current measurement.

A hybrid tuning circuit for continuous-time sigma-delta analog-to-digital converter

Abstract: A hybrid tuning circuit is used consisting of a digital finite state machine and an analog tuning circuit to effectively keep the RC product of the continuous time integrator constant across process, temperature, supply, and sampling rate variations. Since the implementation is continuous, the tracking is more accurate than traditional techniques. Using a carefully chosen clocking scheme, the technique gets rid of inter-symbol interference in the feedback DAC. The technique does not use a reference frequency, thereby eliminating the need for a user to identify a reference frequency.

Systems and methods for multi-channel analog to digital conversion

Abstract: Systems and methods for analog to digital conversion that may be implemented using a digital to analog converter (DAC) to provide negative feedback to cancel signals at the input of an analog to digital converter (ADC), and that may be used to extend the effective dynamic range of an ADC. The systems and methods may be implemented in multi-channel environments.

Analog to digital converter with dither

Abstract: An analog to digital converter is provided comprising an array of capacitors for sampling an input, each capacitor having at least one associated switch for controllably connecting a terminal of the capacitor to a first reference voltage or to a second reference voltage; and a sequence generator for generating a sequence of bits, wherein during sampling of the input onto the array of capacitors an output of the sequence generator is supplied to the switches of a first group of capacitors to control whether a given capacitor within the first group is connected by its associated switch to the first reference voltage or to the second reference voltage.

Optimal index-bit allocation for dynamic post-correction of analog-to-digital converters

Abstract: Signal processing methods for digital post-correction of analog-to-digital converters (ADCs) are considered. ADC errors are in general signal dependent, and in addition, they often exhibit dynamic dependence. A novel dynamic post-correction scheme based on look-up tables is proposed. In order to reduce the table size and, thus, the hardware requirements, bit-masking is introduced. This is to limit the length of the table index by deselecting index bits. At this point, the problem of which bits to use arises. A mathematical analysis tool is derived, enabling the allocation of index bits to be analyzed. This analysis tool is applied in two optimization problems, optimizing the total harmonic distortion and the signal-to-noise and distortion ratio, respectively, of a corrected ADC. The correction scheme and the optimization problems are illustrated and exemplified using experimental ADC data. The results show that the proposed correction scheme improves the performance of the ADC. They also indicate that the allocation of index bits has a significant impact on the ADC performance, motivating the analysis tool. Finally, the optimization results show that performance improvements compared with static look-up table correction can be achieved, even at a comparable table size.

Gain error correction in an analog-to-digital converter

Abstract: An error correction circuit for use with an analog-to-digital converter (ADC) comprising correction capacitance means and switching means coupled to the correction capacitance means. The switching means being coupled to ground and to a plurality of reference voltages and being arranged to couple a bottom plate of the correction capacitance means to ground during a sample phase of the ADC and to one of a plurality of reference voltages during a hold phase of the ADC.

Programmable dual input switched-capacitor gain stage

Abstract: A switched-capacitor gain stage suitable for use with a pipelined analog to digital converter (“ADC”) is capable of processing two or more input channels. The analog input voltages from the multiple channels are concurrently sampled (every other clock phase), and the gain stage processes the samples using a double sampling technique, generates residual voltage samples (every clock phase), and generates digital outputs for the multiple channels in an alternating manner. The gain stage provides equal input loading for the input stages, which enhances the performance of the ADC.

Digital SQUID sensor based on SFQ technique

Abstract: For high sensitive measurements of small magnetic fields a Digital SQUID is superior to conventional analog SQUIDs in terms of dynamic properties, but recent realizations as single-flux-quantum (SFQ) circuit suffers from high complexity. A new kind of Digital SQUID as a full digital sensor device with the advantage of a small number of Josephson junctions and a large slew rate was developed. The circuit consists of basic SFQ cells and an internal digital feedback loop. The operation with a bidirectional clock signal ensures a decreased effort on superconducting electronics. The SFQ/dc converter and an additional voltage driver provides a processable digital output signal for hybrid systems including semiconductor electronics. The sensor circuit was simulated, optimized and fabricated in niobium technology. From investigation of dynamic properties of the circuit we expect a flux slew rate in the gigahertz range.

Time-interleaved analog-to-digital converter and high speed signal processing system using the same

Abstract: A time-interleaved analog-to-digital converter stores in a correction information memory, correction information required to correct an error between signals output by a plurality of N analog-to-digital converters in advance. At this time, in order to enable acquisition of data required for a correction processing within a short period of time, a signal generator causes the plurality of N analog-to-digital converter to input a calibration signal including a plurality of signal components, each of which is positioned at a desired frequency in a bandwidth in which N/2 times of a sampling frequency Fs is defined as an upper limit, the signal components appearing in a bandwidth in which half times of the sampling clock frequency Fs is defined as an upper limit by sampling the analog-to-digital converters. A correction information calculating unit carries out a spectrum analysis relevant to analog-to-digital converted signals output by the plurality of N analog-to-digital converters in response to the calibration signal, thereby obtaining an amplitude and a phase of a plurality of signal components, newly obtaining the correction information, based on the amplitude and phase, and updating contents of the correction information memory in accordance with newly obtained correction information.

Mismatch shaped analog to digital converter

Abstract: A mismatch shaped analog to digital converter. The novel analog to digital converter includes a first circuit for providing a plurality of reference voltages, a plurality of comparators adapted to compare an input signal with the reference voltages, and a second circuit for randomizing connections between the reference voltages and the comparators. The connections are randomized such that noise caused by mismatch errors is spectrally shaped according to a desired noise-shaping characteristic. In an illustrative embodiment, the second circuit includes a noise-shaping circuit comprised of a plurality of Delta-Sigma modulators for generating one or more control signals, and a router for connecting the reference voltages to the comparators in accordance with the control signals. The mismatch shaped analog to digital converter can be used within a Delta-Sigma modulator to shape noise caused by mismatch errors in the feedback digital to analog converter.

Method for search and matching of capacitors for a digital to analog converter of an SAR analog to digital converter

Abstract: The method is described for selecting capacitors from a capacitor array for each bit of a SAR ADC. The process involves selecting a group of capacitors from the capacitor array and determining a weight of the selected group of capacitors. A determination is made if the weights of the selected group of capacitors are substantially equal to their desired values. If the weights are substantially equal to their desired values, the selected group of capacitors is associated with each bit of the SAR ADC. If the weights are not substantially equal to their desired values, a next group of capacitors from the capacitor array is selected for the bits. This process of selecting a group of capacitors and determining their weights is repeated until determined weight for a group of capacitors equals or is closest to the desired values.

Digital control of bridgeless power factor correction circuit

Abstract: A circuit for providing power factor correction includes a bridgeless boost converter circuit and a control circuit receiving an input AC line voltage of the bridgeless boost converter circuit, wherein the control circuit provides a pulse width modulated signal to control the on time of a PFC switch of the bridgeless boost converter circuit. The control circuit also includes a scaling device operable to scale down a bi-polar AC voltage of the input AC line voltage to a uni-polar AC voltage, an analog to digital converter operable to convert the uni-polar AC voltage into digital data and a digital rectifier operable to process the digital data of the uni-polar AC voltage to provide a half-sinusoidal AC signal that is proportional to and in phase with the input AC line voltage for use in providing the pulse width modulated signal.

Rotary flash ADC

Abstract: An analog to digital converter system comprises a multiphase oscillator preferable a rotary oscillator, a sample and hold circuit (psamp), an integrator (iramp), and a time to digtial converter (PFET). The multiphase oscillator has a plurality of phases that are used in the time to digital converter to measure the time of the pulses created by the integrator, Calibration is performed by fragmenting the sample and hold circuit and integrator and performing a closed loop calibration cycle on one of the fragments while the other fragments are joined foi the normal operation of the sample and hold and integrator circuits.

Delta-sigma analog-to-digital converter suitable for use in a radio receiver channel

Abstract: A radio receiver channel includes an analog front end and a digital signal processing section coupled together by an analog-to-digital converter (ADC) having a delta-sigma modulator coupled to a first digital decimation filter, which is coupled to second digital decimation filter, wherein the first decimation filter includes a source of finite impulse response coefficients coupled so as to provide a plurality of coefficients. The delta-sigma modulator includes a loop filter having a plurality of serially coupled integrators, and a multi-bit quantizer coupled to the loop filter; the multi-bit quantizer including an ADC operable to produce a multi-bit digital output signal, the ADC coupled to a DAC having dual DAC feedback loops, and a dynamic element matching function. In one embodiment, the delta-sigma modulator includes a fifth-order loop filter having five serially coupled integrators with a feedback path from the output to the input of the fifth integrator and a feedback path from the output to the input of the third integrator.

Readout integrated circuit (ROIC) for laser detection and ranging (LADAR) system and method for using same

Abstract: Disclosed is a LADAR system and a method for operating same. The LADAR system includes circuitry for generating the electrical signal with an optical signal detector using N discrete samples; a bank of M parallel sample/hold circuit unit cells individual ones of which operate with an associated sample/hold clock, where each sample/hold clock is shifted in time by a fixed or programmable amount Δt relative to a sample/hold clock of an adjacent sample/hold circuit unit cell; and further includes circuitry for sequentially coupling a sampled value of the electrical signal from a first output of individual ones of at least some of the M parallel sample/hold circuit unit cells to an analog to digital converter circuit. Each of the M parallel sample/hold circuit unit cells has a second output for outputting a digital signal for indicating the state (low or high) during a time that the associated sample/hold clock allowing for time of arrival determination. The LADAR system further includes or is coupled to a signal processor for deriving an image of the object and a range to the object based on signals at the first and second outputs. Assuming an effective sample/hold circuit sampling rate of X samples per second, a sampling rate of each of the M parallel sample/hold circuit unit cells can be X/M samples per second.