Showing papers on "AND gate published in 1995"

High speed serial link for fully duplexed data communication

Abstract: A system for converting between parallel data and serial data is described. In the system (10), individual bits of the parallel data (12) are latched into individual registers (117). Each register (117) is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals. The output terminals of the AND gates (110) are connected to an OR gate (115). Using the system, with appropriately phased clocks, the parallel data is converted into serial data.

Self-routing of 100 Gbit/s packets using 6 bit 'keyword' address recognition

Abstract: The authors report the first demonstration of all-optical header recognition and self-routing of ultrafast packets with multibit addresses. A single optical AND gate recognises 6 bit ‘keyword’ codes, allowing self-routing of 100 Gbit/s packets. [This Letter first appeared in print in 1995, issue 17, p.1475–1476, and has been reprinted because of the significance of the corrections.]

Multilevel gate array integrated circuit structure with perpendicular access to all active device regions

Abstract: A multilevel gate array MOS-type integrated circuit structure is described wherein each source, drain, and gate electrode region in the integrated circuit structure is accessible directly through a contact opening formed normal to the plane of the underlying substrate through an overlying insulation layer. The multilevel gate array MOS-type integrated circuit structure of the invention comprises a substrate; a first semiconductor device level comprising one or more first source regions, one or more first drain regions, and one or more first gate electrode regions; and a second semiconductor device level formed over the first semiconductor device level and comprising one or more second source regions arranged to permit access, normal to the plane of the underlying substrate, to an underlying first source region in the first level, one or more second drain regions arranged to permit access, normal to the plane of the underlying substrate, to an underlying drain region in the first level, and one or more second gate electrode regions arranged to permit access, normal to the plane of the underlying substrate, to an underlying gate electrode region in the first level; whereby contact openings may be formed, normal to the plane of the substrate, to each of the source, drain, and gate electrode regions in both semiconductor device levels.

Output circuit for use in a semiconductor integrated circuit

Abstract: An output circuit comprising an output stage and a control signal generator. The output stage is constituted by a first P-channel MOS transistor and an N-channel MOS transistor. The control signal generator generates a signal for driving the gates of the MOS transistors, it comprises a NAND gate, a NOR gate NOR1 and an inverter INV1. The first P-channel MOS transistor of the output stage has a source and a back gate which are isolated in terms of potential. A second P-channel MOS transistor is provided, whose source-drain path is connected between the back gate and gate of the first P-channel MOS transistor incorporated in the output stage.

Language, Thought, and Logic

Abstract: John M. Ellis's Against Deconstruction was hailed as the definitive critique of that complex movement. Now in Language, Thought and Logic Ellis surmounts the impasse and confusion in theory of language to develop a new and strikingly original view. In a field \"which seems to tempt everyone to begin again conceptually at the beginning, \" Ellis observes, many of the initial assumptions made by people who talk and theorize about language are logical mistakes virtually impossible to recover from once made. From this reorientation, Ellis argues that categorization, not syntax, is the most fundamental aspect and process of language, and that neither anything else in language nor, indeed, its purposes can be properly understood until the nature of categorization has been grasped. In the same spirit, he analyzes the notion of grammar and the place of language in human thought. He examines some traditional problems of philosophy in an attempt to show both how they result from an inadequate theory of language and how the view of language developed here leads to a solution of these problems and thus to a redirection of inquiry in the field, and suggests that the process of inquiry in the discipline of linguistics has been fundamentally misdirected because of the logical errors discussed. Supporting these incisive arguments with lucid criticisms of Chomsky and demonstrations of common misreadings of Saussure and Whorf, Ellis establishes a new general picture of linguistic theory and suggests the major implications of that picture. Powerful, rigorous, and innovative, Language, Thought, and Logic makes an important contribution to the understanding of contemporary linguistics.

Programmable function unit as parallel multiplier cell

Abstract: A field programmable gate array (FPGA) includes at least one programmable function unit (PFU) which comprises input lines, output lines, and a look-up table (LUT) for generating various functions in response to a configuration bit stream. A first function is an adder/subtracter in which the first input line provides an add/subtract control signal to a multiplexer coupled to a full-adder. The multiplexer determines whether a data bit or its complement is coupled to the full-adder. A second function is an AND gate coupled to the full-adder in which the first input line provides a data bit to the AND gate. The second function provides a basic cell for a parallel multiplier. Furthermore, the first input line may be used as a control line or a data line for a general logic function, depending on the PFU function.

Structure for cross coupled thin film transistors and static random access memory cell

Abstract: A pair of thin film transistors formed in adjacent layers of polysilicon. The gate of the first TFT and the source, drain and channel regions of the second TFT are formed in the first polysilicon layer. The source, drain and channel regions of the first TFT and the gate of the second TFT are formed in the second polysilicon layer. A dielectric layer is interposed between the first and second polysilicon layers. The first TFT gate overlaps the second TFT drain region in the first polysilicon layer and the second TFT gate overlaps the first TFT drain region in the second polysilicon layer. In another aspect of the invention, two TFTs are incorporated into a SRAM memory cell. The memory cell includes: (i) a bit line; (ii) an access transistor having a first source/drain and a second source/drain, the first source/drain being electrically connected to the bit line; (iii) a parasitic diode formed between the second source/drain of the access transistor and the substrate; (iv) a pull down transistor having a source, drain, channel and gate; (v) a first TFT having a source, drain, channel and gate, the first TFT gate being coupled to a power supply voltage V cc through an active load device comprising a second TFT having a source, drain, channel and gate, and to a voltage not greater than ground through the pull down transistor; and (vi) a storage node for storing a high voltage representative of a first digital data state or a low voltage representative of a second digital state, the storage node being coupled to the bit line through the access transistor, to the substrate through the parasitic diode, to the pull down transistor gate and to the power supply voltage V cc through the first TFT.

Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of different thicknesses and method for its production

Abstract: A read-only-memory cell arrangement comprises memory cells, each having a vertical MOS transistor, in a substrate (21) made of semiconductor material, the various logic values (zero, one) being implemented by gate dielectrics (27, 28) of different thickness. The memory cell arrangement can preferably be produced in a silicon substrate, with a small number of process steps and a high packing density. The memory cell arrangement and a drive circuit for read-out can in this case be produced in an integrated manner.

Manufacture of semiconductor device

Abstract: PURPOSE:To ensure high dielectric strength of an insulating film at an end part of a gate of an insulated gate type semiconductor device. CONSTITUTION:A gate oxide film 12a and a phosphorus-doped conductive polycrystalline silicon film are provided in an element forming region of a silicon substrate 10. The polycrystalline silicon film is selectively removed by the dry etching method to provide a gate electrode 13a. The silicon substrate is thermally oxidized to provide oxide films 13a1, 15b, 16b on a source region forming portion 15 and a drain region forming portion 16 adjacent to the gate electrode and gate oxide film. The oxide film 13a1 is thicker than the oxide films 15b, 16b by about 10nm. Therefore, when each oxide film is removed by the wet etching method, the gate oxide film under the gate electrode is no longer over-etched. Accordingly, when the source region and drain region are provided by diffusion of impurity, distances between the gate electrode and source region and end part of the drain region can be reserved, improving the dielectric strength of the device.

All-optical AND gate operating on 10 Gbit/s signals at the same wavelength using four-wave mixing in a semiconductor laser amplifier

Abstract: Bit error rate measurements on a new optical AND gate using four-wave mixing in a semiconductor laser amplifier and operating on degenerate wavelength input signals are presented. Operation on two 10 Gbit/s data streams with BER <10/sup -10/ shows the potential for using the device in high bit rate optical networks.

Multicell battery system with individually controllable cell bypasses

Abstract: A multicell battery system includes at least two battery cells, and a selective cell bypass for each of the battery cells. Each cell bypass includes a metal-oxide-semiconductor field effect transistor (MOSFET) having a source, a drain, and a gate, a first electrical interconnection from the MOSFET source to a first side of the battery cell, a second electrical interconnection from the MOSFET drain to a second side of the battery cell, and an activation circuit connected to the MOSFET gate. The activation circuit includes an AND gate having as one input an AC square wave signal and as a second input a selection signal, a capacitor connected to the AND gate output signal, and a cascade voltage doubling circuit having an input in communication with a second electrode of the capacitor and an output in communication with the MOSFET gate.

High voltage tolerant CMOS input/output circuit

Abstract: An input/output circuit communicates an external input signal to an internal signal and converts an internal signal to an external output signal. In one embodiment, the input/output circuit has a power supply terminal, and an input terminal that is coupled to an output terminal via a conductor. A pull-up circuit is coupled to the power supply terminal and the conductor, and includes a PMOS transistor having an N-well, where the pull-up circuit is configured to selectively pull-up the output signal. A pull-down circuit is coupled to a ground terminal and the conductor, and is configured to selectively pull-down the output signal. A comparison and logic control circuit is coupled to the power supply terminal and to the conductor, and is configured to compare a supply voltage level to the input signal and is configured to generate an affirmative logic signal when the input signal is greater than the supply voltage level and to generate a negative logic signal when the input signal is less than the supply voltage level. An N-well control circuit is coupled to the power supply terminal, to the conductor and to the pull-up circuit, where the N-well control circuit is responsive to the logic signal, and is configured to output a control N-well signal to control the PMOS transistor N-well voltage.

Depletion mode power MOSFET with refractory gate and method of making same

Abstract: A depletion mode power MOSFET has a gate electrode formed of material that is refractory, or resistant, to high temperature encountered during device fabrication. A depletion channel region which is formed in a base region of a MOSFET and which interconnects the source and drain regions is formed after a high temperature drive to form the base region, but before a gate oxide and gate and source electrodes are formed at lower temperatures. The depletion channel region is thus subjected to reduced temperatures and grows only slightly in thickness, so that it can be easily depleted. The gate oxide, similarly, is subjected to reduced temperatures, and, particularly when made thin, exhibits high insensitivity to radiation exposure.

System and method for disabling or re-enabling PCI-compliant devices in a computer system by masking the idsel signal with a disable or re-enable signal

Abstract: A system and method for disabling and re-enabling PCI-compliant devices in a computer system is disclosed. The system includes a CPU, a host bus coupled to the CPU, a PCI/Host bridge coupled to the host bus, one or more PCI-compliant devices, a PCI bus coupling the PCI/Host bridge and the PCI-compliant devices, and a device, typically in the form of a digital gate, for selectively disabling or re-enabling one or more of the PCI-compliant devices. The disclosed method operates in connection with a computer system having a CPU, a PCI/Host bridge coupled to the CPU and capable of sending an IDSEL signal to the IDSEL input pin of a target PCI-compliant device when attempting a read or write operation on the target PCI-compliant device, and one or more system I/O registers having a CONFIG ENABLE bit that reflects a user's request to disable or re-enable a PCI-compliant device. The method intercepts the IDSEL signal before it reaches the IDSEL input pin of the target PCI-compliant device, provides the intercepted IDSEL signal to the input of a digital gate such as an AND gate, provides a signal corresponding to the CONFIG ENABLE bit to the input of the same digital gate, and delivers the resulting output signal from the digital gate to the IDSEL input pin of the target PCI-compliant device.

Semiconductor device fabrication with planar gate interconnect surface

Abstract: In accordance with principles of the invention, there is provided a new process for semiconductor device fabrication. The disclosed process includes forming field isolation regions on a surface of a silicon wafer, and forming gate oxide regions selectively between the field isolation regions. A gate interconnect material is deposited over the field isolation regions and gate oxide regions. A planar surface is formed on the top of the gate interconnect material. This planarization step may be accomplished by chemical mechanical polishing or some other convenient method such as a resist etch back. After planarization of the gate interconnect material, a uniform thickness photoresist is deposited on the planar surface. A gate interconnect etch pattern is formed on the planar surface using photolithography and the gate interconnect material is etched to match a gate interconnect pattern and the photoresist is removed. Sidewall spacers are provided. A silicide is formed over the top of the gate interconnect and over the diffusion areas.

Automatic synthesis of gate-level timed circuits with choice

Abstract: This paper presents a CAD tool for the automatic synthesis of gate-level timed circuits from general specifications to basic gates such as AND gates, OR gates, and C-elements. Timed circuits are a class of asynchronous circuits that incorporate explicit timing information in the specification which is used throughout the synthesis procedure to optimize the design. Our procedure begins with a textual specification capable of specifying conditional operation, or choice. This specification is systematically transformed to a graphical representation which can be analyzed using an exact and efficient timing analysis algorithm to find the reachable stale space. From this state space, a timed circuit that is hazard-free at the gate-level is derived, facilitating the use of semi-custom components, such as standard-cells and gate-arrays. Because timing information is used to guide the synthesis to reduce circuit complexity while guaranteeing correct operation, the resulting timed circuit implementations are up to 40 percent smaller and 50 percent faster than those produced using other design methodologies.

Some Notes on Power Management on FPGA-Based Systems

Abstract: Although the energy required to perform a logic operation has continuously dropped at least by ten orders of magnitude since early vacuum-tube electronics [1], the increasing clock frequency and gate density of the current integrated circuits has appended power consumption to traditional design trade-offs. This paper explore the usefullness of some low-power design methods based on architectural and implementation modifications, for FPGA-based electronic systems. The contribution of spurious transitions to the overal consumption is evidenced and main strategies for its reduction are analized. The efectiveness of pipelining and partitioning inprovements as low-power design methodologies are quantified by case-studies based on array multipliers. Moreover, a methodology suitable for FPGAs power analysis is presented.

Self-synchronisation scheme for high-speed photonic networks

Abstract: A self-synchronisation technique suitable for both asynchronous and synchronous high speed photonic networks is demonstrated. Experimental results are presented in which an optical AND gate is used to derive a timing reference pulse from a palr of marker pulses positioned at the beginning of a 100 Gbit/s optical packet.

Minimum size integrated circuit static memory cell

Abstract: A semiconductor static memory cell with two cross-coupled inverters and two transmission gates for coupling two bit lines uses all minimum size (gate length and gate width) MOSFETs to achieve minimum area. This minimum dimension is rendered possible by using a higher threshold voltage for the transmission gate MOSFET than the threshold voltage of pull-down MOSFET of the inverter. Different threshold voltages are obtained with selective ion implantation, different gate oxide thicknesses and/or different gate doping.

Optoelectronic parallel processing with surface-emitting lasers and free-space interconnects

Abstract: Parallel optoelectronic processing that uses smart pixel arrays and free space interconnections may provide an attractive alternative to applications that exhibit a large degree of functional parallelism and require massive input/output data rates. Two fine-grain parallel architectures based on two-dimensional arrays of processing elements are discussed in this paper. The logic complexity of the smart pixels ranges from two-input AND and XOR gates for a database filter to multiple-input multiple-output compare-and-exchange modules for a recirculating bitonic sorting unit. Both systems use vertical-cavity surface-emitting lasers as light sources but light detection and logic are implemented differently. The data filter uses GaAs-based phototransistors while the sorting unit requires silicon detectors and CMOS circuitry for its more complex logic. The free-space one-to-one interconnection patterns required between processing planes can be realized with either refractive or diffractive optics and their simplicity and regularity permit easy scale-up. >

Methods for fabricating integrated circuits including openings to transistor regions

Abstract: An MOS transistor for use in an integrated circuit, particularly CMOS integrated circuits, is fabricated with a self-aligning contact and interconnect structure which allows for higher packing density. Self-aligning source and drain contacts overlap the gate but are prevented from short circuiting to the gate by oxide insulation between the source/drain contacts and the gate, and a layer of silicon nitride above the gate. Contacts to the gate are made on top of the gate over the active region of the transistor because the source and drain regions are protected by a hardened layer of photoresist during etching of insulation to expose the gate contact. Source, drain and gate contacts are protected by a layer of titanium silicide so that interconnects are not required to completely cover these areas. Low resistance interconnects are formed of titanium silicide encapulated by a thin film of titanium nitride.

Noncontacting IC card system and gate facility and antenna mechanism

Abstract: A noncontacting IC card system occupying a relatively small area without requiring a provision for a dead zone or unnecessary communication area outside a gate. A transmitting antenna 11 is provided between two contiguous gates i.e., on the inner sides of the gates, and receiving antennas are provided respectively toward the sides opposite to the transmitting antenna of the gates i.e., on the outer sides of the gates. It is thereby not necessary to provide a dead zone between the gates and an unnecessary communication area does not occur outside the gate.

Efficient use of large don't cares in high-level and logic synthesis

Abstract: This paper describes optimization techniques using don't-care conditions that span the domain of high-level and logic synthesis. The following three issues are discussed: (1) how to describe and extract don't-care conditions from high-level descriptions; (2) how to pass don't-care conditions from high-level to logic synthesis; and (3) how to optimize the logic using don't-care conditions. Efficient techniques are given for these three problems which allow the use of large don't-care sets. Results from several examples demonstrate that these techniques are very effective for both area and delay minimization.

A comprehensive study of suppression of boron penetration by amorphous-Si gate in P/sup +/-gate PMOS devices

Abstract: This paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p/sup +/-gate devices. The characteristics and reliability for different gate structures (poly-Si, /spl alpha/-Si, poly-Si/poly-Si, poly-Si//spl alpha/-Si, /spl alpha/-Si/poly-Si, and /spl alpha/-Si//spl alpha/-Si) in p/sup +/ polygate PMOS devices are investigated in detail. The suppression of boron penetration by the nitrided gate oxide is also discussed. The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p/sup +/ polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate. Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate resistance. The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p/sup +/-gate PMOS device for future dual-gate CMOS process. In addition, by employing a long time annealing at 600/spl deg/C prior to p/sup +/-gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate. Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect.

Performance evaluation of asynchronous logic pipelines with data dependant processing delays

Abstract: Among the claims made concerning the advantages of asynchronous logic are that circuits can take advantage of average case (data dependant) speed rather than worst case speed. Whilst this argument can easily be sustained for a single logic stage its extension to systems consisting of many logic stages has not been widely investigated. This paper reports on investigations into the throughput of asynchronous and synchronous pipelines consisting of alternate latches and logic stages where the data dependant delay is a two valued random variable. The extent to which an average case speed of a single stage which is lower than worst case can be translated into higher throughput in an asynchronous pipeline as compared to a synchronous pipeline is found to be restricted by the coefficient of variation of the distribution of data dependant delay, the length of the pipeline, the number of latches used between each logic stage and the number data items in a loop.

Process of fabricating split gate flash memory cell

Abstract: A process of fabricating a split gate flash memory cell first forms a stacked-gate structure on a face of a substrate. The stacked-gate structure includes a tunnel oxide, a polysilicon floating gate, an inter-poly dielectric and a first polysilicon control gate. A drain region is formed into the substrate at one side of the stacked-gate structure, and is self-aligned with the stacked-gate structure. Thermal oxidation is performed to form sidewall oxides on the sidewalls of the stacked-gate structure, and gate oxide on the substrate. A second polysilicon control gate is deposited over the first polysilicon control gate, sidewall oxides and gate oxide, and is connected with the first polysilicon control gate to form a common control gate. A source region is formed in the substrate at another side of the stacked-gate structure, and is self-aligned with the substantially upright portion of the second polysilicon control gate located at the another side of the stacked-gate structure.

Apparatus and method for preventing bus contention during power-up in a computer system with two or more DRAM banks

Abstract: A DRAM circuit is disclosed with circuitry for disabling data output drivers to prevent bus contention during system power-up. The circuitry includes a counter for counting RAS (or CAS) signals, and for disabling the output data drivers until 7 RAS (or CAS) signals are counted. The output of the counter (called Keep Off) connects to each of the tri-state buffer output drivers, through an AND gate. Other inputs to the AND gate may include an output signal Pwrup from a voltage detection circuit, and other enable signals. The counter uses the RAS signals as a clock signal to three D flip-flops. The Pwrup signal also is used as a reset to each of the flip-flops. The Q output of the flip-flops are anded together, to produce a signal which is released when the count reaches 111.

Method of manufacturing a semiconductor device having various types of MOSFETS

Abstract: In a method of manufacturing a semiconductor device including a first MOSFET for a non-volatile memory element, a second MOSFET for an input protecting element and a third MOSFET for a logic circuit element, gate structures of the first to third MOSFETs are formed on a p-type substrate. Then, an n-type impurity is injected in the substrate in self-alignment with the gate structure for the third MOSFET with a first dose amount to form source and drain regions for the third MOSFET. An n-type impurity is simultaneously injected in the substrate in self-alignment with the gate structures for the first and second MOSFETs to form source and drain regions for the first and second MOSFETs. A side wall insulating film is formed on a side wall of each of the gate structures of the thirst to third MOSFETs. An n-type impurity is injected in parts of the source and drain regions of the third MOSFET in self-alignment with the side wall and gate structure with a second dose amount which is higher than the first dose amount.

A novel fabrication process of a silicon field emitter array with thermal oxide as a gate insulator

Abstract: We have successfully developed a fabrication process of a silicon field emitter array with a gate insulator formed by Si/sub 3/N/sub 4/ sidewall formation and subsequent thermal oxidation. This process overcomes some problems in the conventional fabrication, such as high etch rate, low breakdown field, and gate hole expansion arising from evaporation of gate oxide. Therefore, we could improve process stability and emission performance, and also reduce gate leakage current. The optimum process conditions were determined by process simulations using SUPREM-4. The turn-on voltage of the fabricated field emitters was approximately 38 V. An anode current of 0.1 /spl mu/A (1 /spl mu/A) per tip was measured for a 625-tip array at the gate bias of 80 V (100 V), and the gate current was less than 0.3% of the anode current at those emission levels. >

Short circuit power optimization for CMOS circuits

Abstract: An electronic circuit is constructed from a plurality of logic gates, each logic gate including a logic input, a logic output and a pair of power supply inputs, and each logic gate being operable to permit short circuit current to flow between the power supply inputs thereof during a logic level transition at the logic input thereof. A first logic gate (L) and a second logic gate (D) are provided with the output of the second logic gate connected to the input of the first logic gate, and the drive strength of the second logic gate is selected as a function of the short circuit current permitted by the first logic gate.