Showing papers on "Bipolar junction transistor published in 1979"

Quiescent operating point shift in bipolar transistors with AC excitation

Abstract: Describes the rectification response of a bipolar transistor to a small AC signal applied at the base. An RC transmission line model based upon device material and geometrical properties is used to calculate the AC voltage distribution across the emitter. Small changes in the DC operating point at each location across the emitter are then calculated and summed to obtain the terminal characteristic. It is found that the effects of AC crowding and nonlinearity combine to cause DC crowding where the new rectification induced DC current distribution favors the perimeter of the emitter. A model based upon the hybrid pi format is found to be consistent with RF distribution and resultant crowding equations. Also, it is shown how a high frequency rectification response measurement, which, because of severe AC crowding, is edge sensitive, may be used to study recombination near the edge of the emitter.

High performance electrically alterable read only memory (EAROM)

Abstract: The invention is a memory device which includes a metal-nitride-oxide semiconductor (MNOS) insulated gate field effect transistor (IGFET) which is built in series with the base of a bipolar transistor to provide both bipolar current handling capability and bipolar radiation hardness while retaining MNOS memory performance.

A Unified Approach to the Design of Wide-Band Microwave Solid-State Oscillators

Abstract: Present design techniques for broad-band tunable MESFET and bipolar transistor oscillators are indirect and tedious. We present new technique based on negative resistance concepts and a new theorem herein stated and proven. This technique is developed through two design examples a 5.9-12.4-GHz MESFET oscillator and a 2-8.4-GHz bipolar transistor oscillator.

A Modified Ebers-Moll Transistor Model for RF-Interference Analysis

Abstract: This paper develops analytical techniques for the study of nonlinear RF and microwave effects in semiconductor devices. Rectification in p-n junctions is discussed, and a novel large-signal transistor model is developed, based upon modifications to standard Ebers-Moll formulations for bipolar transistors. Use of the models in worst-case analysis is discussed, with ranges of parameters given based on a simplified analysis of rectification in ideal diodes.

Josephson junction with lateral injection as a vortex transistor

Abstract: Long narrow Josephson junctions with current injection to their long (lateral) sides are examined theoretically Injection into a finite number of points as well as distributed injection are considered The external magnetic field effect on the critical current and on the I-V curves is calculated It is shown that the junction with current injection into many points in parallel is an almost complete analog of a conventional semiconductor transistor, the role of electric charge carriers being played by Josephson vortices carrying a single flux quanta The use of a vortex transistor as a circuit element of both analog and digital devices is discussed

Hot-electron camel transistor

Abstract: A transistor is proposed in which hot electrons cross a degenerate semiconductor base region and overcome a potential barrier in the bulk of the semiconductor which forms a collector. Structures in silicon corresponding to this concept have been fabricated using low-energy ion implantation and have given transistor action consistent with hot-electron transport.

Neutron Irradiation for Prevention of Latch-Up in MOS Integrated Circuits

Abstract: Bulk silicon integrated circuits can exhibit latch-up effects which arise from regenerative switching in the parasitic bipolar transistors inherent in the complex circuit configurations. This is especially true for bulk CMOS integrated circuits in which parasitic vertical NPN and lateral PNP bipolars are connected in an SCR fashion. One method for preventing latch-up is lifetime control utilizing neutron irradiation. This work characterizes the long-term annealing of neutron irradiation induced changes in the parasitic bipolar gains of MOS/LSI integrated circuits. A theoretical model, which fits both isothermal and isochronal annealing data, is used to characterize the annealing. Using this model, a procedure has been established for neutron irradiation of LSI integrated circuits which will guarantee that latch-up will not occur during the normal lifetime of the circuits. A detailed discussion of the procedure employed for neutron irradiation of integrated circuits is given, and the results of this procedure applied to several thousand MSI and LSI circuits are described.

Complementary IGFET buffer with improved bipolar output

Abstract: A buffer having a first and second complementary IGFET input inverter connected in series and an output including a bipolar emitter follower with its base connected to the output of the first inverter, a second bipolar transistor connected in series with the emitter follower with its base connected to the output of the second inverter and an IGFET connected between the junction of the bipolar transistors and a voltage supply terminal and with its gate connected to the input of the first inverter. The output IGFET pulls the buffer output up to the supply voltage when the emitter of the emitter follower is at the supply voltage minus V BE .

Characterization of current transport in MNOS structures with complementary tunneling emitter bipolar transistors

Abstract: We have extended the work of previous investigators and studied current transport in thin- (10-20 A) and thick-(80 A) oxide MNOS structures with complementary tunneling emitter bipolar transistors. These devices are fabricated with ion-implanted p-n and n-p junctions to distinguish the dominant carrier species in the insulator. The dominant species in thin-oxide devices is hole transport, comprising about 99 percent of the emitter current. The hole transport is suppressed in the thick-oxide structures, where the dominant carriers are electrons. Electron impact ionization multiplication is observed in thick-oxide structures.

One-dimensional device model of the npn bipolar transistor including heavy doping effects under fermi statistics

Abstract: Carrier transport equations extended to Fermi statistics will be given with characteristic parameters, including heavy doping effect. These equations will be solved numerically by introducing a new method for calculating the parameters. Calculated results will accurately reproduce the significant decrease in transistor current gain with a high impurity concentration at emitter-base junction.

Electrical properties of silicon-implanted furnace-annealed silicon-on-sapphire devices

Abstract: The crystalline quality of s.o.s. layers can be improved near the silicon-sapphire interface by silicon implantation followed by recrystallisation. Device performance on such layers is markedly improved as to n-channel m.o.s.t. noise and leakage current, reverse diode current and lateral bipolar transistor gain. Minority-carrier lifetimes up to 50 ns are deduced.

Power FET inverter drive circuit

Abstract: A half-bridge inverter having first and second power FETs is provided with a high-speed, highly efficient drive circuit for driving the FETs from a single control signal. A single 15 V supply provides energy for charging the gate electrode of the first FET, as well as for a floating source for charging the gate electrode of the second FET. A single bipolar transistor receives the control signal for controlling operation of the first FET, while a current source, a bipolar transistor in series with a resistor, receives the control signal to effect operation of a third bipolar transistor, thereby to control operation of the second FET.

Ion, atom, or molecule sensor - with bipolar transistor with perforated gate as sensor

Abstract: A device for the detection of the presence of ions, atoms and molecules in gases or solutions consists of a semiconductor substrate (1) with an insulating coating (2) (which can be designed as a pn-junction with reversed polarity in the substrate) and a conductive layer. (3)The latter has perforations so that the ions can come into contact with both coatings. If designed as an MOS transistor, the substrate includes doped regions (9) of the opposite conductivity as drain and source, and the perforated coating is used as the gate. The gases or solutions can thus reach the insulator boundary and produce under the gate a change of the work function which can be measured as a voltage, threshold voltage or capacitance change.

Method for making integrated circuit with C-MOS logic, bipolar driver and polysilicon resistors

Abstract: An integrated circuit includes MOS transistors and bipolar transistors, each of both polarity types, in a silicon wafer. High value polysilicon resistors are formed over an outer protective silicon dioxide layer of the silicon wafer, which resistors are rendered conductive by having ion implanted impurities concentrated near the outer surface of the polysilicon body, permitting achievement of close tolerance resistors. The process for making the integrated circuit includes forming a sheet of polysilicon over the entire wafer surface, performing the ion implantation and etching away all but the desired resistor portions of the polysilicon. It also includes heating the wafer to simultaneously anneal the ion implanted polysilicon, form the gate oxide, thicken the oxide over the emitters, and cover the resistor body with a thin protective oxide film.

A fully implanted NMOS, CMOS, bipolar technology for VLSI of analog-digital systems

Abstract: A fully ion-implanted process allows high-density integration of NMOS, CMOS, and bipolar transistors for VLSI of analog-digital systems. Supply voltage can be 20 V. Thresholds are /spl plusmn/1.5 V for p- and n-channel enhancement transistors, respectively. Standard deviation per wafer is 15 mV for the NMOS threshold, while the NMOS gain constant is 30 /spl mu/AV/SUP -2/. The bipolar transistors have a low-resistance base contact. Current gain can be set independently. For current gain=90, the Early voltage if V/SUB A/=110 V. No epi layer, isolation diffusions, or channel stoppers are required. The mask count is 6 for structure definition plus 2 for the masking of implants. The process can be scaled along the learning curve of digital MOS VLSI.

New semiconductor active device: the conductivity-controlled transistor

Abstract: A new semiconductor 3-terminal device has been realised in which a majority-carrier current, flowing in a N+-N-N+ structure, is controlled by a minority-carrier current supplied by a forward-biased P+-N junction. The properties of this device are presented and discussed in terms of a physical model.

Open base bipolar transistor protective device

Abstract: A transistor, used in the switching of current in an inductive load, is protected by a similar transistor connected between collector and base The protective transistor has a lower breakdown voltage than the transistor being protected When the inductive load produces a voltage surge, the protective transistor breaks down first and turns the protected transistor on so that the surge is absorbed in an active transistor not in breakdown and therefore capable of dissipating the surge without damage Since the surge is arrested at high voltage the time required to complete the arrest is shortened

VMOS/Bipolar power switching device

Abstract: A relatively high power switching device is provided via the combination on a common substrate of a VMOS transistor having a gate electrode for receiving a control signal, a drain electrode, and a source electrode, individually connected to the collector and base electrodes of a bipolar transistor, respectively, the collector-emitter current path of the latter being the main current carrying path of the switching device.

Auger recombination in heavily doped shallow-emitter silicon p-n-junction solar cells, diodes, and transistors

Abstract: A rigorous analytic evaluation of an emitter model that includes Auger recombination but excludes bandgap narrowing is presented. It is shown that such a model cannot explain the experimentally observed values of the open-circuit voltage V OC in p-n-junction silicon solar cells. Thus physical mechanisms in addition to Auger recombination are responsible for the experimentally observed values of V OC in silicon solar cells and the common-emitter current gain in bipolar transistors.

Performance limitations of silicon bipolar transistors

Abstract: As the very large-scale integration (VLSI) era begins, the limitations to improving integration in silicon semiconductor technology are being studied, and the integration of many millions of components per single integrated circuit chip is predicted. In this paper we consider some performance limitations of silicon bipolar transistors, assuming our ability to fabricate small geometric devices, by device analysis using an accurate two-dimensional numerical solution of classic semiconductor transport equations. The applicability of mathematical equations used to represent carrier transport in small geometric bipolar transistors and silicon-material parameters, such as bandgap narrowing with doping, ionization coefficients, and lifetime, used in the model has also been considered. The terminal characteristics, the internal behavior, and performance limitations due to voltage and current operating levels of bipolar transistors with emitter depths and basewidths ranging from 0.4 µm to 30 nm have been analyzed. The results of our calculations indicate that the f T and f_{\max} of a bipolar transistor of 1 × 1 µm2emitter size, 30 nm emitter depth, and 30 nm basewidth are about 89 and 6.1 GHz, respectively, at 0.73 mA collector current. Maximum V BC before base-collector junction breakdown at this current level is -2 V. For a device of 1 × 1 µm2emitter size, 100 nm emitter depth, and 100 nm basewidth, the calculated values of f T and f_{\max} are 16.8 and 9.9 GHz, respectively, at a collector current of 0.38 mA.

Transistor logic tristate device with reduced output capacitance

Abstract: A transistor logic tristate output gate or device is provided with active or passive element arrangements coupled between the enable gate on the one hand and the base of the pull down element transistor on the other hand This coupling affords a low impedance route to ground or low potential from the base of the pull down element when the enable gate is at low potential and the output device is in the high impedance third state Miller feedback current at the base of the pull down element transistor is thereby diverted to ground The coupling arrangement affords high impedance to current flow in the opposite direction thereby blocking current flow from the enable gate when the enable gate is at high potential For active discharge of Miller current three transistors are provided in a double inversion series coupling between the enable gate and pull down element Alternately a multiple emitter junction transistor is used For passive element discharge of Miller current a low forward impedance high backward impedance large surface area diode is used

Shootthrough fault protection system for bipolar transistors in a voltage source transistor inverter

Abstract: Faulted bipolar transistors in a voltage source transistor inverter are protected against shootthrough fault current, from the filter capacitor of the d-c voltage source which drives the inverter over the d-c bus, by interposing a small choke in series with the filter capacitor to limit the rate of rise of that fault current while at the same time causing the d-c bus voltage to instantly drop to essentially zero volts at the beginning of a shootthrough fault. In this way, the load lines of the faulted transistors are effectively shaped so that they do not enter the second breakdown area, thereby preventing second breakdown destruction of the transistors.

Signal-processing circuitry with intrinsic temperature insensitivity

Abstract: Signal-processing circuitry including at least two pairs of bipolar transistors with the transistors of one pair being series-connected with the transistors of the second pair, and the second pair being cross-connected from collector-to-base. Other circuitry includes (1) an input arrangement for converting a single-ended input voltage to a complementary pair of currents, (2) a differential emitter-follower providing 2VBEs of level-shifting, (3) means for obtaining an output signal proportional to the square of an input signal, and (4) a simple active rectifier.

Protective circuit for insulated gate field effect transistor integrated circuits

Abstract: A protective circuit for integrated circuits having insulated gate field-effect transistors is disclosed which prevents high potentials resulting from manufacturing, installation, handling, testing or operation from damaging the gate oxide of the field-effect transistors and protective diodes associated with the input of the integrated circuit. The protective circuit includes a first vertical bipolar transistor which has its emitter-to-collector circuit connected in parallel with a first protective diode so that the anode of the diode is connected to the emitter and the input and the cathode of the diode is coupled to the collector and the drain power supply terminal of the field-effect transistors. The inherent distributed resistance of a doped region located within the substrate of the integrated circuit is coupled between the input and the base of the first bipolar transistor. A second lateral bipolar transistor, of an opposite conductivity type than the first bipolar transistor, has its emitter to collector circuit connected in parallel with a series connection of the inherent distributed resistance of the doped region and a second protective diode which is poled in an opposite orientation to the first diode with respect to the input. The cathode of the second diode is connected to the doped region's inherent resistance and the anode of the second diode is connected to the source power supply terminal. The inherent distributed resistance of the substrate of the integrated circuit is coupled between the base of the second transistor and the cathode of a low voltage reverse breakdown diode which conducts in the reverse biased direction during conduction of the second transistor. The emitter of the second bipolar transistor is connected to the input and the collector of the transistor is connected to the anode of the low voltage reverse breakdown diode and the source power supply terminal. The application of a high potential to the integrated circuit which is of sufficient magnitude to rupture the gate oxide of the insulated gated field effect transistors causes conduction of the first or second bipolar transistors before irreversible damage of the protective diodes or the rupture of the gate oxide of the input field effect transistors of the integrated circuit can occur.

Method of making semiconductor devices

Abstract: In a semiconductor device such as a bipolar transistor and a field effect transistor of the type having a substrate, a doped polycrystalline silicon region selectively formed on the substrate and an insulating film overlying the polycrystalline silicon region, the region is shaped as mesa having side surfaces with a negative coefficient of gradient between the substrate and the top of the mesa.

Complementary transistor, inverting emitter follower circuit

Abstract: A complementary bipolar transistor circuit characterized by the same output impedance for positive and negative input voltage transitions, only a single collector path delay between input and output for both senses of input voltage transitions and very low standby power consumption. Provision is made for simultaneously actuating an emitter follower series-connected first pair of complementary transistors with signals having voltage swings which are only a fraction of the V be necessary to forward bias each base-emitter diode of the first pair of transistors. The actuation is accomplished using a second pair of complementary transistors having collector electrodes connected to respective bases of the first pair of transistors of similar kind. One of the remaining electrodes of each of the second pair of transistors are connected to each other. In a driver circuit species of the invention, the bases of the second pair of transistors are connected to each other and receive the input signal. In a logic circuit species of the invention, the emitter of one of the second pair of transistors is connected to the base of the other of the second pair of transistors. NOR logic is performed by connecting additional transistors in parallel with said one of the second pair of transistors, the bases of the additional transistors receiving respective logic input signals. The output from the driver circuit as well as from the logic circuit is derived from the commonly connected emitters of the first pair of transistors. The first pair of transistors conduct only during the transitions of the input signals.

Floating hybrid switch

Abstract: A high-current VMOS transistor having a source connected to a floating reference voltage terminal is switched between conducting and non-conducting states by a low power source including complementary-symmetry FET's. When the VMOS is back biased a low impedance path having a constant predetermined voltage exits between the VMOS source and drain via one of the bipolar transistors. This prevents false triggering of the VMOS if the reference voltage drops below a nominal value. A diode polarized to pass current oppositely from the source drain path and in shunt with the source drain path prevents the VMOS from conducting if the reference voltage rises above the nominal value. The bipolar transistors are shunted by a zener diode to maintain a predetermined voltage across the bipolar transistors, i.e. between the reference voltage terminal and a terminal connected through a load resistor to a power supply terminal.

Bipolar Microwave Linear Power Transistor Design

Abstract: Design considerations for n-p-n bipolar microwave linear power transistors are discussed. Optimization procedures are presented for determining emitter width for a specfic operation frequency, emitter ballasting resistance, and active area geometry based on calculated temperature distributions. A transistor chip designed for 4-GHz operations using these procedures achieved a linear power output of 27.5 dBm at a 1-dB compressed gain of 7 dB with a power added efficiency of 23 percent. Junction temperature rise was limited to 90/spl deg/C.

Self-pulsed microwave power amplifier

Abstract: A pulsed microwave power amplifier for radar transmitters having a class B operated first stage field effect amplifying transistor, which is gate biased to pinch-off in the absence of an input pulse is disclosed. The drain current pulse induced in response to the input RF signal appears as a voltage, which is stepped up through a Ruthroff transformer to turn on a bipolar transistor which switches a gate of a second stage field effect transistor from pinch-off voltage to a voltage corresponding to the drain current substantially equalling 1/2 I DSS to operate class A for the second stage of amplification. A third stage of amplification may be utilized, wherein its field effect transistor, which is also biased to pinch-off is operated in response to the amplified signal.