Showing papers on "Bus network published in 2005"

Local area network of serial intelligent cells

Abstract: A serial intelligent cell (SIC) and a connection topology for local area networks using Electrically-conducting media. A local area network can be configured from a plurality of SIC's interconnected so that all communications between two adjacent SIC's is both point-to-point and bidirectional. Each SIC can be connected to one or more other SIC's to allow redundant communication paths. Communications in different areas of a SIC network are independent of one another, so that, unlike current bus topology and star topology, there is no fundamental limit on the size or extent of a SIC network. Each SIC can optionally be connected to one or more data terminals, computers, telephones, sensors, actuators, etc., to facilitate interconnectivity among such devices. Networks according to the present invention can be configured for a variety of applications, including a local telephone system, remote computer bus extender, multiplexers, PABX/PBX functionality, security systems, and local broadcasting services. The network can use dedicated wiring, as well as existing wiring as the in-house telephone or electrical wiring.

Locomotive power train architecture

Abstract: The present invention is directed to a power control architecture for a vehicle, particularly a locomotive, in which a number of energy sources (105, 111, 115) are connected to a common electrical bus (101, 102) and selectively provide energy to the bus (101, 102) based on the relationship between their respective output voltages and the bus voltage

Scalable DMA remapping on a computer bus

Abstract: A system for addressing bus components comprises a bus controller component that controls access between a CPU and a memory address space. A plurality of bus components connected to said bus controller over a bus are addressable via a memory mapped address within the address space. An address translation table is stored on at least one of the plurality of bus components. The bus translation table stores a translation between a virtual address and a real address.

Comparison of four multi-user quantum key distribution schemes over passive optical networks

Abstract: The performance of four passive optical network topologies in implementing multi-user quantum key distribution is compared. The networks considered are the passive-star network, the optical-ring network based on the Sagnac interferometer, the wavelength-routed network, and the wavelength-addressed bus network. An analysis of the quantum bit-error rate and sifted key rate for each of these topologies is used to determine their suitability for providing service to networks of various sizes.

Direct memory access controller system with message-based programming

Abstract: A data transfer system comprising a first bus interface, a second bus interface, a first-in-first-out memory, a controller and a message unit. The message unit is operable to queue a plurality of data transfer request messages from the first bus interface and the second bus interface. The controller is operable to process each data transfer request message and transfer data between the first bus interface, the first-in-first-out memory and the second bus interface. The controller is configured to calculate error detection codes (EDCs) and chain EDC values.

Design and implementation of CANcentrate: an active star topology for improving fault confinement in CAN networks

Abstract: The Controller Area Network (CAN) is a field bus that is nowadays widespread in distributed embedded systems due to its electrical robustness, low price, and deterministic access delay. However, its use in safety-critical applications has been controversial due to dependability limitations, such as those arising from its bus topology. In particular, in a CAN bus there are multiple components such that if any of them is faulty, a general failure of the communication system may happen. In this document, we propose the design of a new active star topology called CANcentrate 1 . Our design solves the limitations indicated above by means of an active hub which prevents error propagation from any of its ports to the others. CANcentrate exhibits improved fault diagnosis and isolation mechanisms with respect to both all communication systems that rely on a CAN bus and all commercially available CAN communication systems based on a hub. Due to the specific characteristics of our hub, CANcentrate is fully compatible with existing CAN controllers, but requires double links. The present document is devoted to report in detail the work we have done regarding CANcentrate. First, the document compares bus and star topologies, analyzes related work and describes the CANcentrate basics, paying special attention to the mechanisms used for detecting faulty ports. Afterwards, the document explains the reintegration policy the hub performs to deal with transient faults and addresses some issues concerning the cabling length in a star topology. Finally it describes the implementation and tests of a prototype of CANcentrate. 2 .

Blade server system with a management bus and method for managing the same

Abstract: A blade server system with a management bus and method for managing the same. The blade server system includes a connection board and a management module. The connection board is used for modular interconnection, including communication paths for conducting signals including a management bus signal group and a first bus signal group. The management module is used for management of the blade server system using signals including the management bus signal group and the first bus signal group. If a module is detected, the management module selects the detected module through the management bus and acquires module configuration information of the detected module through the first bus signal group. Distribution of power from a power source to the blade server system is determined according to system configuration information including the module configuration information of the module so that the power source is prevented from being overloaded.

Systems and methods for correcting errors in I2C bus communications

Abstract: Systems, methods and media for clearing a hung I2C bus are disclosed. In one embodiment, a monitor monitors the I2C bus data and clock lines and detects if a hung bus occurs. The monitor times packet transactions on the bus to determine if a maximum transaction time has elapsed while the lines are in a hung state. The monitor allows selective reset of individual slave devices and bus masters to clear a hung bus.

Bus arbitration apparatus and bus arbitration method

Abstract: The present invention is to provide a bus arbitration apparatus and a bus arbitration method not reducing data transfer capability as a whole and preventing a loss of transferred data. It performs the arbitration with priority in response to properties of bus masters. It sequentially arbitrates a first hierarchy bus master of which requests are urgent, a second hierarchy bus master that requests data processing in real time, and a third hierarchy bus master that is neither a first hierarchy bus master nor a second hierarchy bus master sequentially.

Node for a bus network, a bus network and a method for configuration of the network

Abstract: Inter alia, the invention provides a node ( 16 ) for a bus network, which has a bus controller ( 30 ) having a receiving and transmitting circuit arrangement ( 32 ) and having a bus connection for transmitting and receiving messages via the bus ( 14 ), and has a node identification set device ( 34, 30 ) for setting a node identification, on the basis of which the node ( 16 ) can respond via the bus ( 14 ) and/or the node can be identified in the network and/or on the basis of which messages sent from the node and/or message contents can be identified and/or on the basis of which messages which are relevant for the node and/or message contents can be identified. The invention provides that the node ( 16 ) has at least one set input connection ( 42 ) which is associated with the node identification set device and is separate from the bus connection, and that the node identification set device ( 34, 30 ) can be activated by application of a set signal to the set input connection ( 42 ) to receive a nominal node identification via the set input connection and/or the bus connection, and to set this nominal node identification as the node identification.

Method and apparatus for constructing wired-and bus systems

Abstract: A large multimaster I 2 C bus system is partitioned into smaller bus segments. The bus segments are connected by bridges that isolate the segments and direct selected transactions and commands between the segments. By programming address bitmaps that are internal to each bridge, transactions can pass through the bridges so that the various bus segments appear to be one logical bus. Because each bridge implements address filtering so that transactions are selectively forwarded from one side of the bridge to the other based on the contents of an internal address bitmap, I 2 C slave addresses can be arbitrarily populated on either side of the bridge. Duplicate I 2 C slave addresses can be also used on different segments of a single logical I 2 C bus system. Masters on one segment can reach devices connected to the same bus segment and can also reach devices with duplicate addresses on other bus segments by using a tunnel command addressed to a bridge.

Network Management Appliance

Abstract: A network management appliance comprising a central bus element; a plurality of network management modules each coupled to the central bus element; a server element coupled to the central bus element a network interface for interfacing the central bus element with a network to be managed; and wherein network management functions executed by the network management modules are remotely accessible through the server element via the network interface.

Apparatus, system, and method for bus link width optimization of a graphics system

Abstract: A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.

Network topology discovery

Abstract: A method of assigning device identification in a switched network, and the resulting switched network, includes designing a network having a design topology made up of network devices, constructing a network from the designed network and discovering the actual topology of the constructed network. The discovered topology is compared with the design topology to assign identifications to network devices of the constructed network.

Method and apparatus of reducing transfer latency in an SOC interconnect

Abstract: Embodiments of the invention are directed to a method and apparatus for reducing transfer latency in a system on a chip, the system on a chip comprising a bus master, a bus slave and an arbiter, wherein the bus master, bus slave and arbiter are in electronic communication therebetween. A request is transmitted from the bus master to the arbiter, wherein a priority signal is associated with a latency requirement. The arbiter reviews the latency requirement prior to transmitting the request to the bus slave and determines whether to elevate the priority signal. The request signal is then transmitted from the arbiter to the bus slave. The bus slave fulfills the request and transmits a response to the request, wherein the transmission includes the priority signal.

Resolving the fairness issues in bus-based optical access networks

Abstract: Packet-based optical access ring is becoming a promising solution in metropolitan networks. Its performance depends mainly on how optical resource sharing takes place among the different competing access nodes. This network architecture has mostly been explored with regard to synchronous transmission, i.e., slotted wavelength-division multiplexing (WDM) ring. However, in this paper, we focus on the performance of asynchronous transmission-based networks with variable packet sizes. Analytical models are presented in an attempt to provide explicit formulas that express the mean access delay of each node of the bus-based optical access network. We prove that in such a network, fairness problems are likely to arise between upstream and downstream nodes sharing a common data channel. Furthermore, we show that sharing the channel's available bandwidth fairly but arbitrarily between access nodes, as in slotted WDM rings, does not resolve the fairness problem in asynchronous system. In this regard, we exhibit the inherent limitations of the token bucket access rate-based algorithm once applied to asynchronous transmission bus-based networks. To alleviate the aforementioned problem, we device a new strategy called traffic control architecture using remote descriptors. The proposed solution is based on a preventive mechanism to grant access to the shared resource. As illustrated in this paper, the proposed solution alleviates the performance degradation and the resource underutilization, while achieving fairness among bus nodes.

A genetic algorithm based bus scheduling model for transit network

Abstract: In this paper we present an optimization model for bus scheduling. This model constitutes one of the three major components of a solution approach for solving the transit network design problem. The problem of scheduling can be defined in the following general terms: Given the origin destination matrix for the bus trips for design period, the underlying bus network characterized by the overlapping routes, how optimally to allocate the buses among these routes? The bus scheduling problem is solved in two levels. In the first level, minimum frequency of buses required on each route, with the guarantee of load feasibility, is determined by considering each route individually. In the second level, the fleet size of first level is taken as upper bound and fleet size is again minimized by considering all routes together and using GAs. The model is applied to a real network, and results are presented.

Serial bus system

Abstract: A serial bus system for data communication between devices according to a master-slave protocol has a data bus connecting master and slave devices and a shared clock system arranged to provide a shared-clock signal to the master and slave devices. The master and slave devices are arranged to derive device-individual clock signals which are synchronized with data received on the data bus, from the shared-clock signal and a data-timing indication on the data bus.

Optimizing bus transit network with parallel ant colony algorithm

Abstract: This study develop an optimization model for bus transit network based on road network and zonal OD. The model aims at achieving minimum transfers and maximum passenger flow per unit length with line length and non-linear rate as constraints. The coarse-grain parallel ant colony algorithm (CPACA) is used to solve the problem. To effectively search the global optimal solution, we use a heuristic pheromone distribution rule, by which ants' path searching activities are adjusted according to the objective value. Parallel ACA is carried out for shortening the calculation time. The model is tested with survey data of Dalian city. The results show that an optimized bus network with less transfers and travel time can be obtained, and the application of CPACA effectively increases the calculation speed and quality.

Logical-to-physical lane assignment to reduce clock power dissipation in a bus having a variable link width

Abstract: A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, clock buffers not required to drive active data lanes are placed in an inactive state to reduce clock power dissipation.

System and method for tunneling standard bus protocol messages through an automotive switch fabric network

Abstract: When a bus protocol message arrives on a connecting node (28) a bus driver in the node captures the message and stores it into a message buffer where the message can be further processed by a tunneling application. Each received bus protocol message is broken, or combined, to suit the available packet size of the underlying transmit (28) layer of the switch fabric network. Data portions such as message identification, sequence number, port number, bus data type, and data length are reserved in each data packet. If the message is being broken down, the sequence number is used to differentiate the broken segments of the bus protocol message. The bus data type is used to indicate the type of protocol data being transmitted over the switch fabric (22).

System and method for notification of arrival of bus or other vehicle

Abstract: A system and method for detecting the proximity of a bus or other transportation. Each bus is equipped with a transmitter, typically radio-frequency (RF), that broadcasts as the bus travels. As the bus and transmitter come within range of corresponding receivers, the receivers will detect the transmitter and will indicate that the bus is approaching. The receivers can be placed at the bus stop, and can also be carried by passengers so that they can be notified of the approaching bus before actually having to go to the bus stop. n various embodiments, the transmitters are implemented using radio-frequency identification (RFID) tags, Bluetooth, and other known RF technologies. Preferably, the transmitters will transmit an identifier that indicates the bus route or specific bus, and the receivers are programmed to only indicate the presence of selected buses.

Bus system with multiple modes of operation

Abstract: An apparatus and a computer-implemented method for processing data in a bus system component. The bus system component is configured to operate in one of an endpoint mode and a root complex mode. Responsive to configuring the bus system component to operate in endpoint mode, the data is processed through the bus system component according to an endpoint process. Responsive to configuring the bus system component to operate in root complex mode, the data is transferred through the bus system component according to a root complex mode. In an illustrative example, the bus system component is a peripheral control interconnect express component.

Information Processing Apparatus Having Multiple Processing Units Sharing Multiple Resources

Abstract: A technique for improving usage efficiency of a shared resource and improving processing capacity in an information processing apparatus, without increasing the transmission rate or the bit width of a bus is disclosed. Multiple bus interfaces are connected to at least one shared resource. The multiple bus interfaces are connected to a multi-layer bus respectively. Furthermore, data buffers for holding read data and write data respectively are provided for each bus interface. An arbiter arbitrates access requests from the respective bus interfaces, and the shared resource reads and writes data in response to the access request which has been given an access right.

Method for operating a packet based data network

Abstract: A method for operating a packet based data network (21; 31), the data network (21; 31) comprising a multitude of nodes (A, B, C, D) and a shared data bus (22; 32), wherein at least some of the nodes (A, B, C, D) add traffic to the data bus (22; 32), and wherein the upstream nodes (A, B, C, D) reserve data transfer capacity of the data bus (22; 32) for downstream nodes (A, B, C, D) by means of a fairness mechanism, is characterized in that at least some of the nodes (A, B, C, D) drop traffic from the data bus (22; 32), and that said fairness mechanism takes into account the drop traffic at downstream nodes (A, B, C, D). The inventive method allows a better bandwidth utilization and uses available resources more efficiently.

Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures

Abstract: In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consumption and performance of the system. We use a genetic algorithm and design an appropriate cost function which optimizes the solution on the basis of its power consumption and performance. The evaluation of our approach using a set of multiprocessor applications show that an average reduction of the energy consumption by 60% over a single shared bus architecture. Our results also show that it is beneficial to simultaneously assign bus frequencies and performing bus partitioning instead of performing them sequentially.

Systems and methods for analyzing bus data

Abstract: Systems and methods for analyzing transactions on a bus. A software module can cause a trace packet to be generated and sent out on a bus to an invalid address. The trace packet triggers a protocol analyzer and permits the bus data flowing on the bus when the software module detected a problem to be analyzed. The trace packet causes the protocol analyzer to trigger even though the bus protocol is normal and the protocol analyzer would not otherwise trigger. The trace packet can be used to analyze and debug communications flowing on a bus when the software module detects a problem.

Rapid vehicle bus network activity

Abstract: An apparatus and method for rapidly providing activity on a vehicle network bus (12,Fig.1) includes a node (TCU 14, Fig.1) having a bus connection to the vehicle network bus. The node (TCU 14, Fig.1) includes a Rapid Response Stack (24, Fig.1) loaded with the predetermined message to respond to any network bus request before the application is up and running. A true stack is loaded with real messages from the application once it is booted up and running on the node, whereupon the application subsequently responds to network bus requests using the true stack instead of the Rapid Response Stack.

Method for the non-bitrate-dependent encoding of digital signals on a bus system

Abstract: To provide a bus system having a plurality of stations that are coupled together by an arrangement of lines and each have a transceiver and a control unit, a microcontroller, or the like, and to specify a method of encoding a digital message on a bus system in which method the digital message comprises at least one part that is encoded in a non-bitrate­dependent manner and by means of which method it becomes possible for a transceiver or a system base chip to independently receive and analyze the data transmitted on the bus line, and in particular, in accordance with the method, to individually wake a bus node by means of a given wake-up message even when the part of the bus node that is on standby at the relevant point in time does not have an accurate timer and also does not have any knowledge of the bitrate at which the data is transmitted on the bus, provision is made, under the bus system according to the invention, for at least one transceiver (100) to comprise means for the non-bitrate-dependent analysis of digital signals and, under the method according to the invention, for the value of a bit in that part of the message that is encoded in a non-bitrate­dependent manner to be represented by the lengths of successive dominant and recessive phases.

Bitwise arbitration on a serial bus using arbitrarily selected nodes for bit synchronization

Abstract: A plurality of nodes are coupled via a serial data bus A transition from a first state to a second state is repeatedly transmitted onto the bus from a node arbitrarily selected from the plurality of nodes and is defined as the bit master. One or more of the nodes transmits onto the bus dominant and recessive states at a first predetermined time after each transition. The transmitted states represent respective dominant and recessive bits of an attempted message. The plurality of nodes detect dominant and recessive states of the bus at a second predetermined time after each transition. Any of the one or more nodes that transmits a recessive bit at the first predetermined time and detects a dominant bit at the second predetermined time ceases transmission of bits onto the bus.