Showing papers on "Chip published in 1982"

A Regular Layout for Parallel Adders

Abstract: With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.

Coherent Spread Spectrum Systems

Abstract: Synchronous Pseudonoise Coded Spread Spectrum Systems. PCM Code Formatting and Spectra. Modulation of Multi-channel Coherent Systems. Phase-Locked Loops. Tracking With Suppressed Carrier Loops. Coherent Detection of Coherent Modulated Signals. An Introduction to Linear Pseudonoise Sequences. PN Code Spread Spectrum Systems. PN Code Acquisition and Lock Detection Performance. PN Code Tracking. Gold Codes. Symbol Synchronizatin for PSK. Appendixes. Index.

Error Probability for Direct-Sequence Spread-Spectrum Multiple-Access Communications--Part II: Approximations

Abstract: Approximations are obtained for the average probability of error in an asynchronous direct-sequence spread-spectrum multiple-access communications system. Both binary and quaternary systems are considered, and the chip waveforms are allowed to be arbitrary time-limited waveforms with time duration equal to the inverse of the chip rate. The approximation is based on the integration of the characteristic function of the multiple-access interference. The amount of computation required to evaluate this approximation grows only linearly with the product of the number of simultaneous transmitters and the number of chips per bit. The accuracy of the approximation is extremely good in most cases, but it can be improved, if necessary, by an application of a series expansion. Numerical results are presented for specific chip waveforms and signature sequences.

Effect of scaling of interconnections on the time delay of VLSI circuits

Abstract: Effect of scaling of dimensions, i.e., increase in chip size and decrease in minimum feature size, on the RC time delay associated with interconnections in VLSIC's has been investigated. Analytical expressions have been developed to relate this time delay to various elements of technology, i.e., interconnection material, minimum feature size, chip area, length of the interconnect, etc. Empirical expressions to predict the trends of the technological elements as a function of chronological time have been developed. Calculations of time delay for interconnections made of poly-Si, WSi 2 , W, and Al have been done and they indicate that as the chip area is increased and other device-related dimensions are decreased the interconnection time delay becomes significant compared to the device time delay and in extreme cases dominates the chip performance.

Effect of Scaling of Interconnections on the Time Delay of VLSI Circuits

Abstract: Effect of scaling of dimensions, i.e., increase in chip size and decrease in minimum feature size, on the RC time delay associated with interconnections in VLSIC's has been investigated. Analytical expressions have been developed to relate this time delay to various elements of technology, i.e., interconnection material, minimum feature size, chip area, length of the interconnect, etc. Empirical expressions to predict the trends of the technological elements as a function of chronological time have been developed. Calculations of time delay for interconnections made of poly-Si, WSi/sub 2/, W, and Al have been done and they indicate that as the chip area is increased and other device-related dimensions are decreased the interconnection time delay becomes significant compared to the device time delay and in extreme cases dominates the chip performance.

Electronic Chip-In-Place Test

Abstract: Electronic Chip-in-Place Test (ECIPT) is a design approach and a test methodology for VLSI packages containing multiple semi-conductor chips. Shift register latches are used in such a way that each chip on a package is accessible for testing from the package pins without in-circuit probing. A means is therefore provided, whereby tests generated for a chip can be reapplied at the package level. The ECIPT methodology additionally provides a mechanism for simplified tests of failures associated with interchip wiring and chip I/O connections.

Quadruply self-aligned stacked high-capacitance RAM using Ta 2 O 5 high-density VLSI dynamic memory

Abstract: A new one-transistor, one-capacitor RAM cell structure called a Quadruply Self-Aligned Stacked High Capacitance (QSA SHC) RAM is proposed as a basic cell for a future one-million-bit VLSI memory. This cell consists of a QSA MOSFET and a Ta 2 O 5 capacitor stacked on it. By this cell, the ultimate cell area 3F \times 2F can be realized with sufficient operating margin. Here, F is the minimum feature size. The basic cell was fabricated and its operation was experimentally verified. The leakage current of Ta 2 O 5 film was small enough for the storage capacitor dielectric. Using a 3F \times 4F cell and a 4F pitch sense amplifier, a one-million-bit memory was designed with a 2-µm rule. A cell size of 6.5 × 8 µm2, and a chip size of 9.2 × 9.5 mm2were obtained. The access time, neglecting the RC time constant of the word line, was estimated to be about 170 ns. Based on this design, it is argued that a future one-million-bit memory can be realized by QSA SHC technology with a 2-1-µm process. The mask set of the 1-Mbit RAM was actually fabricated by an electron-beam mask maker. A photomicrograph of the 1-Mbit RAM chip patterned by the mask set is shown. This chip was patterned not to get an operating sample but to show an actual chip image of the future 1- Mbit RAM. The area of each circuit block including storage array can be seen in this chip image.

Orthogonal code division multiple access communications systems

Abstract: An orthogonal code division multiple-access communications system comprised of a plurality of transceivers respectively employing orthogonal noise code mate pairs of a type having autocorrelation functions upon detection which when linearly added together compress into a lobeless impulse and wherein the same single time slot is utilized by all of the users in the system. Each user is assigned a different unique noise code pair consisting of code mate pairs that are selected from a subset of multiplexed noise codes whose cross-correlation function value is equal to zero at a time when all the code mate pairs compress to an impulse, i.e. τ=0. The described arrangement enables random access, or direct call-up, to be accomplished with no interference between the users while using different noise codes for each user.

A conduction-cooled module for high-performance LSI devices

Abstract: The advent of LSI chip technology makes possible significantly increased performance and circuit densities by means of large-scale packaging of multiple devices on a single multi-layer ceramic (MLC) substrate. Integration at the chip and module levels has resulted in circuit densities as high as 2.5×10 7 circuits per cubic meter, with the necessity of removing heat fluxes on the order of 100 kW/m 2 . This paper describes the development and implementation of a novel packaging concept which meets the stringent and highly interactive demands on cooling, reliability, and reworkability of LSI technology. These requirements resulted in an innovative packaging approach, referred to as the thermal conduction module (TCM). The TCM uses individually spring-loaded “pistons” that contact each chip with helium gas, the conducting medium for removing heat efficiently. A dismountable hermetic seal makes multiple access possible for device and substrate rework, while ensuring mechanical and environmental protection of critical components. A wide range of thermal, mechanical, and environmental experiments are described with analytical and computer models. The one-dimensional approach used in the previous paper by Chu et al. is extended to three-dimensional computer modeling. Simulations of expected chip temperature distributions in the IBM 3081 Processor Unit are discussed. Enhanced thermal performance of the advanced packaging concept for future applications is also indicated.

Signal processing algorithms and architectures

Abstract: The advent of the Very Large Scale Integration (VLSI) technology has provided the ability to construct large systems on a single silicon chip. This dissertation is concerned with exploiting this ability to design a powerful signal processing chip capable of efficiently implementing such popular algorithms as the discrete Fourier transform, ladder filters and associated matrix algebra operations. The latter include Givens rotations and Cholesky factorization. The goal of the present work is to efficiently map algorithms onto architectures by maintaining a close link with the theoretical basis of a particular signal processing method. It is shown that all of the algorithms considered can be cast into a mathematical framework involving generalized vector rotations. Such rotation operations provide a natural description of the algorithms and the computational complexity measured in terms of these elementary operations is much lower than in terms of the usual measure of total number of multiplications. Thus, unlike present day signal processing computers which emphasize rapid multiplication, the signal processing architectures in this thesis are based on the ability to perform vector rotations in generalized coordinate systems. It is shown that the CORDIC algorithm of Volder provides a convenient implementation of vector rotations with only simple components such as adders, registers and shifters. Unfortunately, throughput is severely compromised owing to the need for performing special operations to account for the limited region of convergence and spurious scale constants inherent to the method. New techniques to circumvent these problems with no additional hardware and only a marginal speed penalty are described. Further speed enhancements through the use of a newly developed method known as hybrid CORDIC are discussed. Additionally, floating point CORDIC (FLORDIC) algorithms that are conceptually simpler than their fixed point counterparts are developed and the connection of CORDIC to the convergence computation methods is shown. The architecture of a dual CORDIC block chip is described for a target application of real time speech analysis. The resulting chip is shown to have a higher throughput per area than conventional chips based on fast multiplications. This is attributed to the close match of the present chip to the algorithms. Large mesh connected processor architectures for matrix factorization are developed which are also closely matched to the algorithms. Individual processing elements in the mesh are based on CORDIC operations, in fact on the aforementioned signal processing chip. Finally, a new technique for signal detection in additive Gaussian noise is developed with a view towards ease of implementation. It is based on ladder filters and may be implemented using the signal processing chip mentioned above.

Semiconductor integrated circuit memory device with both serial and random access arrays

Abstract: A semiconductor memory device of the single-chip MOS/LSI integrated circuit type has both serial access and random access means on the same chip. When the device is addressed for random access then data input or output is the same as in dynamic RAM operation, but if the address is for serial operation then access is different. For a serial read operation a row containing the addressed data is transferred to a shift register coupled to the random access array, and the shift register is clocked out. For serial write, data is clocked into the shift register then this row of data is transferred into the columns of the array.

Repairable multi-level overlay system for semiconductor device

Abstract: A multi-level integrated circuit packaging system having a primary support frame, an array of secondary support frames mounted in said primary support frame and an array of single chip carriers associated with each secondary support frame. An integrated circuit is encapsulated in each single chip carrier, which may be a variety of carrier types which has an insulated wiring pattern with EC wells and delete lands. The secondary and primary support frames also have EC pads so that a change capability exists to any electrical signal path terminating on the chip.

Adaptive acquisition of multiple access codes

Abstract: An adaptive acquisition technique is disclosed for enabling the initial acquisition of a received coded signal in a direct sequence spread spectrum system using multiple access codes for code division multiplexing. In order to obtain code synchronization by initial acquisition, correlation of a received code with a reference code is performed by an adaptive serial search over the code phase uncertainty which compares the measured signal correlation levels with two thresholds fixed to have a constant difference. During code signal acquisition, the thresholds are increased each time the measured correlation level exceeds the upper threshold, by an amount which equals the difference between the correlation level and the current upper threshold. Initial code signal acquisition is indicated when the detected correlation level raises the threshold levels to a point after which no further correlation measurements exceed the lower threshold. In this manner, false code signal synchronizations normally caused by autocorrelation sidelobes during strong signal reception, are reduced with little degradation in the low signal performance of the system.

Electronic Chip-In-Place Test.

Abstract: Electronic Chip-in-Place Test (ECIPT) is a design approach and a test methodology for VLSI packages containing multiple semi-conductor chips. Shift register latches are used in such a way that each chip on a package is accessible for testing from the package pins without in-circuit probing. A means is therefore provided, whereby tests generated for a chip can be reapplied at the package level. The ECIPT methodology additionally provides a mechanism for simplified tests of failures associated with interchip wiring and chip I/O connections.

Magneto-optic display

Abstract: A display adapted to be helmet-mounted or used for projecting and having the multi-mode capability of full three-primary color displays; gray scale or halftones; stereo imagining; image processing; split-screen operation; blink comparator; see-through, heads-up viewing; and night-vision intensification combined with alpha-numerics. A bulb in a reflective housing illuminates a plastic diffusion screen to create a light beam. An electronic alterable, random-access storage display chip is placed in line with the emerging beam. The display chip comprises a film sandwich configuration consisting of a sheet polarizer, a magneto-optic chip with addressible alterable areas, and a sheet polarization analyzer. Signals received from a radio link are applied through a cable and connectors to the chip. By driving the chip as a function of the desired display, the display is impressed on the beam of light which may then be split and passed through appropriate focusing lenses for viewing or projected. Multiple beams, multiple display chips, and multiple layered chips with filtering are employed to create various operating modes.

Electronic timepiece with temperature compensation

Abstract: An electronic timepiece having a quartz crystal oscillator circuit as a timebase signal source is provided with a temperature compensation system to compensate timebase signal frequency deviations with temperature, all components of the system being incorporated in the timepiece IC chip. The system is based on a temperature-sensitive voltage stabilizer circuit whose output voltage is current-converted to control the frequency of a temperature-insensitive oscillator circuit. Date generated on the basis of the latter oscillator frequency is applied to compensate the timebase signal frequency, by a capacitor switching technique.

A redundancy circuit for a fault-tolerant 256K MOS RAM

Abstract: A multiple word/bit line redundancy technique introduced into a fault-tolerant 256K MOS RAM is described. The address of the defective lines are stored in spare decoders and defective lines are replaced by redundant lines. New electrically programmable elements are used in these spare decoders. Yield improvement as a result of the implementation of the redundant lines is discussed, and a detailed description of the redundancy circuit design is given. The redundancy occupies less than 10 percent of the whole chip area of the 256K MOS RAM. The good (defect-free) chip functions without any degradation of speed and power caused by the redundancy, while the power consumption and access time increases in the repaired chip are 10 and 25 percent, respectively.

Adaptive differential pulse code modulation

Abstract: A differential pulse code modulation system is made adaptive to quantization noise in a way which permits variable-rate operation as either a conventional R-bit embedded code or as a combination of a conventional R-bit code and a further explicit noise code with instantaneous quantization. Additional improvement in signal-to-noise ratio is attainable by using a noninstantaneous variable-bit allocation procedure for equal-length sampling blocks with an averaged fixed bit code.

Means and method for disabling access to a memory

Abstract: An integrated circuit chip having a digital memory is provided wherein direct access to at least a portion of the memory is prevented. Contact pads having coupling lines to couple the contact pads to the memory bus are provided. A security code can be programmed into a portion of the memory during wafer probe and test. When the integrated circuit chip is removed from the wafer the coupling lines between the contact pads and the memory bus are destroyed since the coupling lines are made to extend off of the chip.

An ultralow power 8Kx8-bit full CMOS RAM with a six-transistor cell

Abstract: A fully static 8K word by 8 bit CMOS RAM, with a six-transistor CMOS cell structure to achieve an extremely low standby power of less than 50 nW has been developed. A 2 /spl mu/m, double polysilicon CMOS process was utilized to realize a 19/spl times/22 /spl mu/m cell size. Redundance technology with polysilicon laser fuses was also developed for improving fabrication yield with relatively large chip size, i.e. 5.92/spl times/7.49 mm. In addition, for reducing operational power dissipation while maintaining fully static operation from outside on the chip, an internally clocked low-power circuit technology using row address transition detectors was employed, which results in only 15 mW operational power at 1 MHz by cutting off all DC current paths. The RAM offers an 80 ns address access time.

One-chip microcomputer

Abstract: A one-chip microcomputer including a central processing unit, a direct memory access controller and a random-access memory. In a DMA operation mode, data stored in the random-access memory is transmitted through common terminals to the exterior by means of a time-division control circuit or registers for parallel-serial conversion. The common terminals are also used for a CPU operation mode.

A-to-D converter of the successive-approximation type

Abstract: An integrated-circuit analog-to-digital converter of the successive-approximation type formed on a single monolithic chip. The converter is made by a diffusion process wherein certain portions of the chip are formed with normal-mode linear transistors, and other portions are formed with inverted mode I 2 L transistors. The normal-mode transistors provide a switchable current-source DAC, a set of three-state output buffers, and a comparator. The inverted mode transistors provide an internal clock and successive-approximation control circuitry for the DAC. The chip also includes a voltage reference to provide for absolute analog-to-digital conversions.

Integrated circuit chip carrier

Abstract: An integrated circuit chip carrier is made of plastics material, such as glass/epoxy printed circuit board material, and comprises a base and a side wall attached to the top surface of the base to define a chip mounting cavity. Conductor tracks on the base extend from connecting pads inside the cavity to connecting points on the periphery of the carrier. The chip carrier can be fabricated as one of an array of such carriers for subsequent separation.

Monolithic Dual-Gate GaAs FET Digital Phase Shifter

Abstract: The design, fabrication, and characterization of a fully monolithic FET digital phase-shifter circuit is described. The circuit is designed around a unique dual-gate FET structure operating as a switchable single-pole, double-throw amplifier. Each 2.5 X 3.0-mm chip has one bit (e.g., 22.5°, 90°, etc.) of phase control. The circuit, which includes all dc bypass circuitry on-chip, features thin-film lumped element capacitors and inductors, air-bridge crossovers and interconnects, via-hole frontside grounding, and integral beam leads. The fabrication of these elements is described in some detail. The phase-shifter circuit gives a peak gain of 3 dB across a 10-percent bandwidth in X-band. A method of achieving continuous phase and amplitude control using a 90° bit chip is described. Finally, phase performance of a four-bit digital phase shifter realized by cascading four monolithic active phase-shifter chips is reported.

Manufacture of semiconductor device

Abstract: PURPOSE:To automatically dispose the chip securing position at the center of a chip mounting part when securing the chip via molten wax by forming wavy pattern on the outer periphery of the chip mounting part of a support, e.g., ceramic package, leadframe, etc. CONSTITUTION:A chip mounting metallized part 14 having a wave pattern is formed on the outer periphery of the first ceramic layer 12 of a laminated ceramic package 10. The part 14 is formed by sequentially plated with Ni and Au on the primary later, e.g., tungsten or the like. A solder preform 24, a semiconductor chip 26 are sequentially placed and heated treated on the part 14 in the cavity. When the chip is placed eccentrically with respect to the part 14, the solder operates with surface tension in the molten state, thereby returning the chip to the center of the part 14. Thus, the chip can be automatically disposed at the center fixedly.

A 4-valued ECL encoder and decoder circuit

Abstract: The authors present the prototype of a 4-valued ECL encoder and decoder circuit that has been designed as a test chip for the realization of 4-valued cells to be used in interconnection networks. The hardware implementation of such a network in a SIMD or a MIMD computer architecture leads to a significant reduction of the number of wires. Static and dynamic characteristics are presented together with results on the propagation of 4-valued signals. Noise margins are compared for 2-valued and 4-valued versions.

A single-chip NMOS analog front-end LSI for modems

Abstract: Presents a fully integrated analog front-end LSI chip which is an interface system between digital signal processors and existing analog telecommunication networks. The developed analog LSI chip includes many high level function blocks such as A/D and D/A converters with 11 bit resolution, various kinds of SCFs, an AGC circuit, an external control level adjuster, a carrier detector, and a zero crossing detector. Design techniques employed are mainly directed toward circuit size reductions. The LSI chip is fabricated in a 5 /spl mu/m line double polysilicon gate NMOS process. Chip size is 7.14/spl times/6.51 mm. The circuit operates on /spl plusmn/5 V power supplies. Typical power consumption is 270 mW. By using this analog front-end LSI chip and a digital signal processor, modern systems can be successfully constructed in a compact size.

Monolithic analog adaptive equalizer integrated circuit for wide-band digital communication networks

Abstract: This equaliser is presented with particular emphasis on architecture and performance. To reduce the size, cost, and power dissipation, and to improve the operation speed and performance, this equalizer IC employs many techniques such as all analog signal processing with parallel updating the weights and eliminating the offset according to the least mean-square algorithm, MOS VLSI fabrication process and switched capacitor technique. As the key building blocks, low- and high-speed MOS operational amplifiers and four-quadrant analog multipliers are specially developed. The 16 mm/SUP 2/ chip providing 5 taps operates on /spl plusmn/5 and 10 V power supplies with power dissipation of 570 mW. The maximum data rate is more than 200 kHz. For the linear adaptive equalizer configuration operating at a data rate of 100 kHz, the residual RMS distortion and convergence time are measured to be -40 dB and about 2 ms (200 iterations), respectively, when a binary signal with an initial RMS distortion of 40 percent (-7.96 dB) is applied.

High-voltage subscriber line interface LSIs

Abstract: A high-voltage BORSHT LSI family for an all solid-state subscriber line interface circuit in a digital local switching system has been developed. The family consists of a 320 V dielectrically isolated RTLSI, a 60 V bipolar BSH-LSI, and a CMOS control LSI. Ringing, reverse, and network-test functions were implemented in the RT-LSI chip using a high-voltage current-controlled p-n-p-n-switch integration technology. Battery feed, supervision, and hybrid functions have been integrated into the BSH-LSI chip using a high-precision analog bipolar process technology. The CMOS logic LSI performs a digital interface function with the PCM highway, as well as a control function for the other LSIs. Using this BORSHT LSI family along with a codec, it has become possible to make a low-cost and small-size subscriber line interface circuit for central office use.

Universal leadless chip carrier mounting pad

Abstract: The present disclosure describes a universal leadless chip carrier mounting pad layout for an interconnection medium such as a printed circuit board, which accommodates a wide range of chip carrier sizes. Thus, there is eliminated the traditional method of providing custom pad layouts homologously configured as to numbers of pads and their arrangement, in specific chip carriers. The universality of the present pad layout makes it especially desirable for prototype designs, and integrated circuit chip "burn in" and test procedures.