Showing papers on "Clock gating published in 1996"

Monolithic phase-locked loops and clock recovery circuits : theory and design

Abstract: Featuring an extensive 40 page tutorial introduction, this carefully compiled anthology of 65 of the most important papers on phaselocked loops and clock recovery circuits brings you comprehensive coverage of the field-all in one self-contained volume. You'll gain an understanding of the analysis, design, simulation, and implementation of phase-locked loops and clock recovery circuits in CMOS and bipolar technologies along with valuable insights into the issues and trade-offs associated with phase locked systems for high speed, low power, and low noise.

Apparatus and method for dynamic central processing unit clock adjustment

Abstract: In a computer system having a cpu, a device for dynamic cpu clock adjustment. The device is comprised of a clock pulse generator for generating a clock frequency. The clock frequency is coupled to the cpu and is used by the cpu to synchronize and pace its internal operations. The clock frequency generated by the generator is variable over a range. A controller is coupled to the clock pulse generator, for adjusting the clock frequency from the clock pulse generator over the range. The controller interfaces with the computer system through an interface coupled to the controller. Through the interface, the controller communicates with the computer system or cpu and determines a load placed on the cpu. The controller adjusts the clock frequency generated by the clock pulse generator such that the clock frequency increases when the load on the cpu increases and the clock frequency decreases when the load on the cpu decreases, dynamically adjusting the clock frequency in response to the load on the cpu.

Phase-locked delay loop for clock correction

Abstract: A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference input clock signal or which produces a selected phase relationship to the reference clock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference input clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference input clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference input clock/output clock relationship. In one form of the invention, an inventer adapted to invert one of the reference input clock and output clock signals, and a divide by N circuit for lowering the clock frequency while roughly adjusting the delay.

Method and apparatus for reducing power consumption in digital electronic circuits

Abstract: An integrated circuit with power conservation includes a number of functional blocks, each of which includes digital circuitry and at least one output control line, and a power controller coupled to the control lines. The output control lines develop clock control signals based upon a functional block's knowledge of the direction of data flow. The power controller reduces power by deactivating functional blocks that are not needed as indicated by the clock control signals. More specifically, a system with power conservation includes a number of functional blocks capable of processing data, each of the functional blocks including a modulated clock input and N+1 clock control lines which reflect the direction of data flow, where N is a number of neighbors of a particular functional block, and a clock controller having an input clock, the clock controller being coupled to the modulated clock inputs and the clock control lines of the functional blocks. The clock controller is operative to modulate the input clock in accordance with the signals on the clock control lines to provide modulated clocks to each of the plurality of functional blocks. A method for reducing power consumption includes the steps of: a) receiving control signals from a number of functional blocks; b) selectively deactivating a particular functional block upon a request from that functional block or from another functional block; and c) activating the particular functional block upon a request from another functional block.

Compensation of chip to chip clock skew

Abstract: Information about the relative phase relationship of the clocks of two chips that are connected with an inter-chip connection is used to adjust the clocks. In the method proposed by the invention, transitions between a good data transfer behaviour to a worse data transfer behaviour are detected as a function of the variable clock delays which delay the chip clock, and a clock delay value between the transitions is chosen. Thus, an optimization of data transmission is achieved, and it can be shown that with this procedure, the clock skew is accurately compensated as well. Additionally, a method for quantifying the variable clock delay, which consists of a multitude of delay elements arranged in a delay chain, is given. In order to do this, the number of delay elements necessary for a delay of half a clock cycle is determined. Thus, a connection between the length of a clock cycle and the delay caused by one delay element is established. With this method of quantifying delays, it is possible to transmit information about the value of the variable clock delay between chips. It is also possible to transmit this information to a central clock adjustment unit, which is especially advantageous in a multi-chip system. The central clock adjustment unit can calculate the appropriate delay values for each chip and thus synchronize a multutude of chips.

Memory having a plurality of external clock signal inputs

Abstract: A method and apparatus for operating a synchronous memory from a plurality of external clock signals is described. By providing external system, read, and write clock signals, a memory is operated by delaying operational clock signals, such as read and write clock signals, with respect to a system clock signal in order to reduce the apparent access time of the synchronous memory and/or to increase setup time to the synchronous memory. The delay of the read and write clock signals with respect to the system clock signal may be accomplished through a phase-lock-loop or delay-lock-loop which is off-chip with respect to the integrated circuit synchronous memory. Delay circuitry may be employed for operating one or more than one synchronous memories.

Optimal clock skew scheduling tolerant to process variations

Abstract: A methodology is presented in this paper for determining an optimal set of clock path delays for designing high performance VLSI/ULSI-based clock distribution networks. This methodology emphasizes the use of non-zero clock skew to reduce the system-wide minimum clock period. Although choosing (or scheduling) clock skew values has been previously recognized as an optimization technique for reducing the minimum clock period, difficulty in controlling the delays of the clock paths due to process parameter variations has limited its effectiveness. In this paper the minimum clock period is reduced using intentional clock skew by calculating a permissible clock skew range for each local data path while incorporating process dependent delay values of the clock signal paths. Graph-based algorithms are presented for determining the minimum clock period and for selecting a range of process tolerant clock skews for each local data path in the circuit, respectively. These algorithms have been demonstrated on the ISCAS-89 suite of circuits. Furthermore, examples of clock distribution networks with intentional clock skew are shown to tolerate worst case clock skew variations of up to 30% without causing circuit failure while increasing the system-wide maximum clock frequency by up to 20% over zero skew-based systems.

Method and apparatus for clock synchronization across an isochronous bus by adjustment of frame clock rates

Abstract: A mechanism for adjusting the frame clock used by an audio DSP or other functional unit to transfer data to the rate at which data is transferred across an isochronous bus. According to one embodiment of the present invention, there is provided a mechanism for monitoring the level of data in a data buffer. The data are transferred to the buffer from the audio DSP, and then out the buffer across the isochronous bus, such as a Universal Serial bus. If the level in the buffer is too high, the audio DSP is filling the data buffer too quickly. If the data level in the buffer is too low, then the audio DSP is not providing the data quickly enough. The frame clock on the audio logic which is used to generate and transfer the data to the buffer is adjusted. Thus, if the level in the buffer is too high, the frame clock will be slowed; if the level in the buffer is too low, the rate of the frame clock will be increased. More particularly, there is provided a programmable clock divider which receives as input a master clock used by the audio DSP for computational purposes, and from which the frame clock is derived. Responsive to the level of data in the buffer, the programmable clock divider will adjust the rate of the frame clock.

A portable clock multiplier generator using digital CMOS standard cells

Abstract: High frequency clock rate is a key issue in today's VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 /spl mu/m CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps.

Configurable drive clock

Abstract: An apparatus and method which provides specified hold times for communication signals transmitted from a processing device that is capable of operating at different frequencies, to external devices, is provided. The apparatus includes a clock multiplier which generates an internal clock signal which is a multiple of an external clock, a ring oscillator, which provides a number of outputs of the same frequency as the internal clock, but at fixed phase offsets from the internal clock, and clock select circuitry, which selects one of the outputs from the ring oscillator, depending on the speed of the internal clock, to be used as a drive clock signal for a bus unit. Selection of one of the phase offset outputs provides for a specified hold time regardless of the internal clock speed of the processing device.

Sizing of clock distribution networks for high performance CPU chips

Abstract: In a high performance microprocessor such as Digital's 30O MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a complex grid with multiple drivers. The large capacitance of this distribution grid together with the high clock frequency results in substantial power dissipation in the chip. In this paper, we describe techniques to size the interconnect segments (thus reducing their capacitance) of the distribution network while meeting certain design goals. These techniques place no restrictions on the topology of the network being sized, and have been successfully used on very large examples.

Clock supply permission/inhibition control system

Abstract: Each buffer circuit in a clock driver is enabled/disabled in accordance with clock drive control information set in a clock drive control register. Since the clock drive control information set in the register is programmable, the clock signal lines of a plurality of PCI devices can be selectively driven. Therefore, clock supply to unused PCI devices can be stopped, so that wasteful power consumption can be reduced.

Utilizing the retiming-skew equivalence in a practical algorithm for retiming large circuits

Abstract: The introduction of clock skew at an edge-triggered flip-flop has an effect that is similar to the movement of the flip-flop across combinational logic module boundaries, and these are continuous and discrete optimizations with the same effect. While this fact has been recognized before, this paper, for the first time, utilizes this information to find an optimal retiming. The clock period is guaranteed to be at most one gate delay larger than the optimal clock period found using skew alone; note that since skew is a continuous optimization, it is possible that the optimal period may not be achievable. The method views the circuit hierarchically, first solving the clock skew problem at one level above the gate level, and then using local transformations at the gate level to perform retiming for the optimal clock period. The solution is thus divided into two phases. In Phase A, the clock skew optimization problem is solved with the objective of minimizing the clock period, while ensuring that the difference between the maximum and the minimum skew is minimized. Next, in Phase B, retiming is employed and some flip-flops are relocated across gates in an attempt to set the values of all skews to be as close to zero as possible.

Adjusting clock frequency and voltage supplied to a processor in a computer system

Abstract: A method and apparatus for adjusting the clock frequency and voltage supplied to an integrated circuit. First, a signal is sent to the clock, and in response, the clock lowers the clock frequency supplied to the integrated circuit. The clock sends a signal to the voltage regulator whereupon the voltage regulator reduces the voltage supplied to the integrated circuit.

Clock reproduction circuit and elements used in the same

Abstract: A clock reproduction circuit for reproducing a data clock from a data signal is disclosed. The clock reproduction circuit includes a voltage controlled oscillator, a phase detector, a frequency error detection circuit and a charge pump whose output is controlled by the outputs of the phase detector and the frequency error detection circuit. A VCO clock output from the voltage controlled oscillator is synchronized with the data clock by the feedback loop consisting of these elements. The frequency error detection circuit detects a frequency error between the VCO clock and the data clock by detecting changes in the phases of the VCO clock at the transition edges of the data signal. Analog and digital frequency error detection circuits are disclosed. Further, improved circuit elements in the clock reproduction circuit are disclosed.

Dynamic latching device

Abstract: A high-performance dynamic flip-flop circuit implementation. The dynamic flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (319). The flip-flop comprises a delay block (317) coupled to a clock input (305). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (440) of the delayed clock output (319) follows a rising edge (444) of a clock signal after a delay period (448). The flip-flop clocks in new data at a data input (305) in response to the clock input (310) during this delay period (448). Data is held in a storage block (360). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

Clock skew optimization for peak current reduction

Abstract: The presence of large current peaks on the power and ground lines is a serious concern for designers of synchronous digital circuits. Current peaks are caused by the simultaneous switching of highly loaded clock lines and by the signal propagation through the sequential logic elements. In this work we propose a methodology for reducing the amplitude of the current peaks. This result is obtained by clock skew optimization. We propose an algorithm that determines the clock arrival time at each flip-flop in order to minimize the current peaks while respecting timing constraint. Our results on benchmark circuits show that current peaks can be reduced by more than a factor of two without penalty on cycle time and average power dissipation. Our methodology is therefore well-suited for low-power systems with reduced supply voltage, where low noise margins are a primary concern.

Hierarchial clock distribution system and method

Abstract: A microelectronic circuit includes a plurality of circuitry blocks and sub-blocks, a clock driver, an electrical interconnect that directly connects the clock driver to the sub-blocks, and balanced clock-tree distribution systems provided between the electrical interconnect and circuitry in the sub-blocks respectively. A method of producing a hierarchial clock distribution system for the circuit includes determining clock skews between the clock driver and the sub-blocks respectively. Delay buffers are selected from a predetermined set of delay buffers having the same physical size and different delays, with the delay buffers being selected to provide equal clock skews between the clock driver and the distribution systems respectively. Each delay buffer includes a delay line, and a number of loading elements that are connected to the delay line, with the number of loading elements being selected to provide the required clock delay for the respective sub-block.

EMI reduction for a flat-panel display controller using horizontal-line based spread spectrum

Abstract: A graphics controller uses spread-spectrum techniques to modulate the pixel clock over a range of frequencies, reducing the maximum intensity of EMI emissions. When the clock input to the graphics controller is replaced with a modulated clock, the image on a CRT is distorted. Distortion is avoided by only modulating the clock to the flat-panel LCD interface. The vertical and horizontal timing signals for both the CRT and the LCD are generated from the un-modulated clock. Using the un-modulated clock for these critical timing signals ensures that each horizontal line is displayed for the same period of time. Brighter and dimmer lines are thus avoided. A second embodiment modulates the clocks to the CRT and LCD, reducing emissions for both interfaces. Even the timing signals use the modulated clock. The frequency sweep of the modulated clock is reset at the end of every horizontal line. Thus all lines are displayed for the same period, although the transfer of pixels within a line are modulated. Even though the pixel clock is modulated while pixels are written to the displays, the same sequence of modulations is repeated for each line. Thus pixels from different lines are aligned and zig-zag and wiggle distortions seen when simple asynchronous modulation is applied to all clocks is avoided.

Common-mode output sensing circuit

Abstract: A common-mode sensing circuit (504) of a clocked differential amplifier (602) includes a refresh circuit (604) which precharges a capacitance during a first clock phase (P 1 ) and discharges the capacitance to drive the outputs (514, 516) of the differential amplifier (602) to a desired common-mode voltage (V AGO ) during a second clock phase, which increases the output loading during the second clock phase (P 2 ). A load balancing circuit (606) selectively switches a load to the outputs (514, 516) during the first clock phase (P 1 ) to match the load produced by the refresh circuit (604) during the second clock phase (P 2 ).

Method and apparatus for reducing power consumption in a mobile radio communication device

Abstract: Methods and systems for generating timing signals in remote units which can be used in a radiocommunication system are described. A high accuracy clock can be used to provide a timing reference signal for a processor in the remote unit during times when highly accurate timing signals are required. During periods of low activity, the high accuracy clock can be turned off and a low accuracy clock can be used to generate the reference timing signals for the processor. Periodically, the accuracy of the low accuracy clock can be checked by determining a number of low accuracy clock pulses which are generated between system timing signals created based upon the high accuracy clock pulses. In this way, when the low accuracy clock is relied upon to create the system tuning signals, the accuracy is sufficient to enable the processor to recognize when it is time to again power up the high accuracy clock. Moreover, checking the accuracy of the low accuracy clock enables the processor to provide error compensation signals to a real time clock function which relies upon the low accuracy clock pulses for determining a current time.

Useful-skew clock routing with gate sizing for low power design

Abstract: Instead of zero-skew or assuming a fixed skew bound, we seek to produce useful skews in clock routing. This is motivated by the fact that negative skew may allow a larger timing budget for gate sizing. We construct a useful-skew tree (UST) such that the total clock and logic power (measured as a cost function) is minimized. Given a required clock period and feasible gate sizes, a set of negative and positive skew bounds are generated. The allowable skews within these bounds and feasible gate sizes form the feasible solution space of our problem. We use a merging segment perturbation procedure and a simulated annealing approach to explore various tree configurations. This is complemented by a bi-partitioning heuristic to generate appropriate connection topology and take advantage of useful skews. Experimental results have shown 11% to 22% total power reduction over previous methods of clock routing with zero-skew or single fixed skew bound and separately sizing logic gates.

Low power, testable dual edge triggered flip-flops

Abstract: Power dissipation is an important parameter in the design of VLSI circuits, and the clock network is responsible for a substantial part of it (up to 50%). Two main approaches have been suggested to reduce clock dissipation: clock gating and low power flip-flops. In this article we address the latter. We demonstrate that the usage of double edge triggered flip-flops results in a power reduction of 50% in the clock net, and in a reduction of up to 45% inside the flip-flops. Furthermore, we consider other flip-flop parameters, like setup and hold times, propagation delay and testability.

Clock distributing circuit

Abstract: A clock distributing circuit, that comprises a clock distribution output circuit for inputting an external clock, outputting a first clock that synchronizes with the external clock, and distributing the first clock to each of load circuits, and a distributed clock input circuit disposed on input stages of all or part of the load circuits and adapted for inputting the first clock and outputting a second clock that synchronizes with the input clock, wherein one of the clock distribution output circuit and the distributed clock input circuit includes a phase difference-voltage converting circuit for converting the phase difference between the input clock and the output clock into a voltage, and a voltage control type delay circuit for delaying the input clock corresponding to an output voltage of the phase difference-voltage converting circuit and for outputting the delayed input clock.

Phase detector for clock synchronization and recovery

Abstract: A clock recovery circuit employing a phase-locked loop design includes an N-to-1 multiplexer (MUX) coupled to a series of N latches which allows data to sampled at a frequency N times that of the clock. Incoming data is latched by each of the N latches, where each latch is clocked at a different phase of the clock signal such that the phase of the clock provided to the nth latch is shifted nT/N, where T is the period of the clock and n is an integer from 1 to N. The output terminals of the series of N latches are coupled to associated ones of input terminals of the N-to-1 MUX. The selection of MUX input terminals is controlled by the clock signal such that the incoming data signal is reconstructed at the output terminal of the MUX. In this manner, the incoming data signal is effectively sampled at N times the clock speed.

Method and apparatus for removing timing hazards in a circuit design

Abstract: A computer system is programmed with logic for automatically removing timing hazards from a circuit design. More specifically, the computer system is programmed with logic for automatically detecting and resolving clock gating as well as clock division timing hazards from the circuit design. In one embodiment, the computer system is further programmed with logic for logically organize timing hazards into levels, after the clock gating timing hazards have been resolved, and then resolving clock division timing hazards recursively. In one adaptation, the computer system is a component of a hardware emulation system.

Clock rate compensation for a low frequency slave device

Abstract: A slave device having clock rate compensation circuitry for low frequency operation. The slave device is coupled to a bus having a first operating frequency yet uses a slave clock signal having a frequency less than the first operating frequency. The slave device includes a bus clock driver circuit coupled to a bus clock interface for a bus clock signal. A slave controller state machine is clocked by the slave clock signal and accordingly operates at less than the first operating frequency. The clock rate compensation circuitry receives the bus clock signal, a data signal, and the slave clock signal, and synchronizes bus events for the state machine. The clock rate compensation circuitry also asynchronously begins a bus clock signal stretching period.

A robust single phase clocking for low power, high-speed VLSI applications

Abstract: Power dissipation is becoming a prime design constraint in VLSI systems. The new key words for evaluating a design's performance are low power and high speed. This requires an overall system design review that considers suitable algorithms, architectures, circuits, and technology. In synchronous systems, the clocking network sets the frame that contains the whole design. It must be simple and robust. Power consumption in the clock distribution network has usually been a substantial part of the system total power consumption. New true single phase latches and flip flops are presented that are slope-insensitive, fast, and have data dependent power consumption. Flip flops are presented that work between DC and 1.7 GHz clock frequencies in a 1 /spl mu/m CMOS technology. Methods are given that result in power saving in the clock system by reducing the clock rate by half for the same data throughput on the system level.

Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew

Abstract: An integrated top-down design methodology is presented in this brief for synthesizing high performance clock distribution networks based on application dependent localized clock skew. The methodology is divided into four phases: (1) determining an optimal clock skew schedule composed of a set of nonzero clock skew values and the related minimum clock path delays; (2) designing the topology of the clock distribution network with delays assigned to each branch based on the circuit hierarchy, the aforementioned clock skew schedule, and minimizing process and environmental delay variations; (3) designing circuit structures to emulate the delay values assigned to the individual branches of the clock tree; and (4) designing the physical layout of the clock distribution network. The clock distribution network synthesis methodology is based on CMOS technology. The clock lines are transformed from distributed resistive capacitive interconnect lines into purely capacitive interconnect lines by partitioning the RC interconnect lines with inverting repeaters. Variations in process parameters are considered during the circuit design of the clock distribution network to guarantee a race-free circuit. Nominal errors of less than 2.5% for the delay of the clock paths and 7% for the clock skew between any two registers belonging to the same global data path as compared with SPICE Level-3 are demonstrated.

Glitchless clock switching circuit

Abstract: A glitchless clock switching circuit utilizes a clock select input signal to determine which one of a plurality of clock input signals will be switched onto a clock output line. The clock select input signal and the multiple clock input signals may be completely asynchronous to each other.