Showing papers on "Diffusion capacitance published in 1992"

Scaling the Si MOSFET: from bulk to SOI to bulk

Abstract: Scaling the Si MOSFET is reconsidered. Requirements on subthreshold leakage control force conventional scaling to use high doping as the device dimension penetrates into the deep-submicrometer regime, leading to an undesirably large junction capacitance and degraded mobility. By studying the scaling of fully depleted SOI devices, the important concept of controlling horizontal leakage through vertical structures is highlighted. Several structural variations of conventional SOI structures are discussed in terms of a natural length scale to guide the design. The concept of vertical doping engineering can also be realized in bulk Si to obtain good subthreshold characteristics without large junction capacitance or heavy channel doping. >

Intermodulation in heterojunction bipolar transistors

Abstract: The modeling of small-signal intermodulation distortion (IMD) in heterojunction bipolar transistors (HBTs) is examined. The authors show that IMD current generated in the exponential junction is partially canceled by IMD current generated in the junction capacitance, and that this phenomenon is largely responsible for the unusually good IMD performance of these devices. Thus, a nonlinear model of the HBT must characterize both nonlinearities accurately. Finally, the authors propose a nonlinear HBT model suitable for IDM calculations, show how to measure its parameters, and verify its accuracy experimentally. >

Large signal modeling of HBT's including self-heating and transit time effects

Abstract: A physically based, large signal heterojunction bipolar transistor (HBT) model is presented to account for the time dependence of the base, collector, and emitter charging currents, as well as self heating effects. The model tracks device performance over eight decades of current. The model can be used as the basis of SPICE modeling approximations, and to this end, examples are presented. A thesis for the divergence of high frequency large signal SPICE simulations from measured data is formulated, including a requisite empirical equation for the base-collector junction capacitance. >

Theory of junction between two-dimensional electron gas and p-type semiconductor

Abstract: The authors develop a theory of the junction between a two-dimensional electron gas and a three-dimensional p-type semiconductor contact. The cut-in voltage of such a junction depends on the density of the 2-D electron gas. Hence, at low currents, the device current varies exponentially with the 2-D gas density. The unique features of such junctions include a very small effective cross section (equal to the product of the thickness of the 2-D gas and the device width) and, hence, a small junction capacitance and a small device current at large current densities. Using a conformal mapping technique, the authors calculate potential and field distributions and find the differential device capacitance as a function of bias. They then calculate the output device characteristics for different gate voltages. The results of a 2-D self-consistent Monte Carlo simulation for such a structure are presented. This simulation clearly shows that electrons and holes are localized in the vicinity of the 2-D electron gas even at high drain biases. >

Method of making a power VFET device using a p+ carbon doped gate layer

Abstract: This is a method of forming a vertical transistor device. The method comprises: forming a n-type source layer 12; forming a p+ carbon doped gate layer 14; forming a gate structure from the gate layer; and forming a n-type drain layer 16 over the gate structure to provide a buried carbon doped gate structure. The buried carbon doped gate structure provides a very small device with favorable on-resistance, junction capacitance, gate resistance, and gate driving voltage. Other devices and methods are also disclosed.

Highly integrated semiconductor memory device with triple well structure

Abstract: A highly integrated semiconductor memory device, such as a DRAM, is provided with a unique triple-well structure which results in reduced junction capacitance of transistors and a smaller body effect. The semiconductor memory device comprises first and second wells of a first conductivity type and a third well of a second conductivity type formed in a semiconductor substrate of the first conductivity type. The first well is formed in the third well and the first well and the second well are connected to receive a ground level Vss well bias voltage and a negative level V BB well bias voltage, respectively. A plurality of MOS transistors of the first conductivity type are formed in the third well and at least two series-connected MOS transistors of the second conductivity type are formed in the first well. A plurality of MOS transistors of the second conductivity type and a plurality of memory cells are also formed in the second well.

Facet engineered elevated source/drain by selective Si epitaxy for 0.35 micron MOSFETS

Abstract: A novel facet-engineered elevated source/drain formation design is presented It is found that the ex situ clean prior to selective Si epitaxial growth (SEG) determines the resulting facets on the SEG-source/drain We show that low angle facets are very advantageous for minimizing parasitic Miller capacitances, while simultaneously grading the source/drain junction near the gate edge and retrieving the source/drain junction from the substrate elsewhere, thus reducing the junction capacitance Further, we show that both a strong current drive (I/sub DS/) increase and a reduction in parasitic junction capacitance can be realized with facet-engineered phosphorus doped SEG-source/drain with no detrimental effects to short channel device behavior >

A self-aligned pocket implantation (SPI) technology for 0.2- mu m dual-gate CMOS

Abstract: The self-aligned pocket implantation (SPI) technology developed features a localized pocket implantation using a gate electrode and TiSi/sub 2/ films as self-aligned masks. This process provides high punchthrough resistance and high current driving capability while suppressing the impurity concentration in the twin well. The drain junction capacitance is decreased by 30% for N-MOSFETs and by 49% for P-MOSFETs, compared to conventional LDD devices. It is found that a dual-gate CMOS device fabricated by the SPI technology achieves high circuit performance. >

Gain compensation circuit

Abstract: A circuit for compensating for GaAs FET amplifier gain variations over a frequency band as a function of temperature. The circuit includes a passive equalizer circuit having a fixed gain over the frequency band and an active equalizer circuit having a gain which varies over the frequency band as a function of temperature. The passive and active equalizers are coupled in series. The active equalizer circuit comprises varactor diodes in a low pass filter arrangement with the bias voltage of the varactor being provided by an external driver controlled by a temperature sensitive thermistor. As the value of the varactor's junction capacitance is increased (as a function of the temperature controlled bias voltage), the cutoff frequency of the low pass filter decreases.

Method for fabrication of a field oxide of the buried inverse t-type using oxygen or nitrogen ion implantation

Abstract: The present invention relates to a semiconductor and a method for fabrication thereof and particularly to a semiconductor having a field oxide having a shape such that the lower part is wider that the upper part. Therefore, according to the present invention, the ion implantation process for forming a channel stop region becomes unnecessary, because of the effect of accurate insulation between the devices and the pn junction area can be decreased, so that the junction capacitance becomes decreased. Furthermore, because LOCOS edge does not coincide with the junction edge, the leakage current due to the damage of the edge is not generated. Because a field oxide is of the buried inverse T-type, the effective width of the device is increased more than that of a mask. Because the bird's beak is not generated, the problem due to the narrow width can be settled.

Design of bipolar imaging devices (BASIS): analysis of random noise

Abstract: A design methodology for a bipolar imaging device, the base-stored image sensor (BASIS), has been established by theoretical analysis and experimental verification for random noise. The random noise in BASIS is dominated by the shot noise in readout and transient reset operation. The theoretical analysis has been carried out by introducing the probability density functions for these operations. The readout noise depends on the base-to-collector junction capacitance C/sub bc/, the emitter common current gain h/sub FE/, the storage capacitor C/sub T/, and the emitter voltage V/sub E/. The reset noise has been confirmed to be given by thermal noise. The theoretical results coincide well with the experimental results obtained by TEG devices. An expression for the S/N ratio has been derived theoretically. It is found that h/sub FE/ should be made as large as possible and (C/sub bc/+C/sub be/) as small as possible to improve the S/N ratio for random noise, where C/sub be/ is the base-to-emitter junction capacitance. >

A Schottky/2-DEG varactor diode for millimeter and submillimeter wave multiplier applications

Abstract: A new Schottky diode is investigated for use as a multiplier element in the millimeter and submillimeter wavelength regions. The new diode is based on the Schottky contact at the edge of a 2-dimensional electron gas (2-DEG). As a negative voltage is applied to the Schottky contact, the depletion layer between the Schottky contact and the 2-DEG expands and the junction capacitance decreases, resulting in a nonlinear capacitance-voltage characteristic. In this paper, we outline the theory, design, fabrication, and evaluation of the new device. Recent results include devices having cutoff frequencies of 1 THz and above. Preliminary multiplier results are also presented.

A Large-Signal Equivalent Circuit Model for Hyperabrupt P-N Junction Varactor Diodes

Abstract: A large-signal equivalent circuit model is presented for a hyperabrupt p-n junction varactor diode (HJVD), suitable for nonlinear CAD and computer simulation A new function is proposed to describe the nonlinear dependence of the junction capacitance on the applied voltage Experimental measurements on several commercial devices are presented, showing excellent agreement with the model proposed, over a very wide range of applied voltages A physical investigation of the doping profile of hyperabrupt p-n junctions is made and a method to determine the doping profile parameters for an assumed type of dopant distribution is presented Finally, validation of the model is demonstrated in two particular applications

Large-signal nonquasi-static model for single and double heterojunction bipolar transistors

Abstract: A large-signal nonquasi-static model for heterojunction bipolar transistors (HBTs) is presented. Using this model, the turn-on and turn-off transient characteristics were simulated. The simulation results obtained using this model and that of Gummel-Poon model are compared with the results obtained numerically. This comparison shows that our model can more accurately predict the device transient performance. The model accuracy can be improved even further if nonquasi-static junction capacitance models are used. Using our model, it will be possible to simulate digital circuits in the gigabit range.

A semi-physical bipolar transistor model for the design of very-high-frequency analog ICs

Abstract: A compact transistor model that is well suited for the design of very-high-frequency analog ICs and advanced narrow-emitter transistors is presented. It takes into account non-quasi-static transistor behavior and HF emitter current crowding as well as emitter-periphery and high-current effects. Modeling of the transit time, the base resistance, and the emitter junction capacitance was improved. Besides the simulation of HF analog ICs, the model proved to be well suited for simulating the switching behavior of high-speed digital ICs. >

Manufacture of semiconductor device

Abstract: PURPOSE: To realize high performance BiCMOS's by a method wherein, after a well of MOS field-effect transistors and an active region of bipolar transistors are formed on a semiconductor substrate, impurities are further doped in a region forming an emitter region of the bipolar transistors. CONSTITUTION: There are selectively formed a first N-type burying layer 12 of high concentration with arsenic As and a P-type burying layer 14 with boron B on one surface of P-type semiconductor substrate 10. Phosphorus P ions are injected into a vertical lower step part of an emitter region of bipolar transistors to form a second N-type burying layer 100a. The second N-type burying layer 100 is diffused upward of the first N-type burying layer 12 by heating. An epitaxial thickness of a MOS transistor part is as it is, and it is possible to enhance frequency characteristics and a current drive force of the bipolar transistors without degrading of characteristics of MOS transistors due to an increase in junction capacitance by a decrease in a thickness of an epitaxial layer.

Base-emitter diffusion capacitance in GaAlAs/GaAs HBTs

Abstract: The voltage dependence of the base–emitter diffusion capacitance in a single heterojunction GaAIAs/GaAs HBT is discussed. It is found that conventional transistor capacitance models are not accurate for these devices. An empirical expression is given which may be used to model this diffusion capacitance.

Effect of cooling on the efficiency of Schottky varactor frequency multipliers at millimeter waves

Abstract: The efficiency of the Schottky diode multiplier can be increased by cooling the diode to 77 K. The main reason for better efficiency is the increased mobility of the free carriers. Because of that the series resistance decreases and a few dB higher efficiency can be expected at low input power levels. At high output frequencies and at high power levels, the current saturation decreases the efficiency of the multiplication. When the diode is cooled the maximum current of the diode increases and much more output power can be expected. There are also slight changes in the I-V characteristic and in the diode junction capacitance, but they have a negligible effect on the efficiency of the multiplier.

Inverter circuit for dc brushless motor

Abstract: PURPOSE: To protect elements against breakdown by preventing instantaneous turn ON of transistors at upper stage section and lower stage section through simple circuitry. CONSTITUTION: A PNP type single or Darlington connection transistor is employed as a high withstand voltage transistor Q 1 at the upper stage section of a semiconductor switch group 1 producing winding current of a brushless motor whereas an NPN type transistor is employed as a transistor Q 2 at the lower stage section. A feedthrough preventive diode 11 is inserted between the collector of the transistor Q 1 and the collector of the transistor Q 2 . This constitution decreases junction capacitance between base and collector each of the upper and lower stage transistors and prevents the upper stage transistor from being turned ON by the function of the lower stage transistor. COPYRIGHT: (C)1994,JPO&Japio

Method of manufacturing a semiconductor memory having an increased cell capacitance in a restricted cell area

Abstract: A semiconductor memory includes at least one memory cell composed of an insulated gate field effect transistor and an associated stacked capacitor which are formed close to each other on a single substrate of a first conduction type. The insulated gate field effect transistor has a source and a drain which are located separately from each other in the single substrate and formed of impurity regions of a second conduction type opposite to the first conduction type. The insulated gate field effect transistor also has a gate formed through a gate insulator on a region between the source and the drain. The gate and the source of the insulated gate field effect transistor are connected to a word line and a bit line, respectively, and the drain of the insulated gate field effect transistor is connected to a first electrode of the stacked capacitor. The memory cell also comprises a first impurity region of the first conduction type formed in the substrate below the stacked capacitor, and a second impurity region of the second conduction type which is formed above the first impurity region in the substrate below the stacked capacitor and which has a junction depth shallower than the depth of the first impurity region, so that a pn junction is formed between the first impurity region and the second impurity region. The second impurity region is connected to the first electrode of the stacked capacitor. With this arrangement, the memory cell has a cell capacitance of based on a sum of a capacitance of the stacked capacitor and a junction capacitance of the pn junction.

Semiconductor device and fabrication thereof

Abstract: PURPOSE: To prevent punching-through from being produced between a source and a drain and hereby reduce parasitic junction capacitance for prevention of delayed operation by constructing a device such that a channel part has surface concentration of satisfactorily low impurity, and a high concentration region is located below the channel part and a lower concentration region than a well is located on the bottom of a source-drain region. CONSTITUTION: There is selectively grown on a p-well 2 of 10 17 cm -3 surface concentration and non-doped epitaxial Si layer 6 or an epitaxial Si layer 6 having about 2×10 15 cm -3 p type low concentration. Then, there is formed by ion implantation a p type channel doping layer 7 having about 2×10 17 cm -3 peak concentration at the depth of about 0.08μm over an entire device region 3. Hereby, threshold voltage is lowered along a channel surface part S 1 to prevent punching-through from being produced between a source region 10s and a drain region 10d in a high concentration region in the vicinity of an intermediate part S 2 . A region S 3 where bottom parts of the source and drain regions make contact gets low impurity concentration to reduce junction parasitic capacitance. COPYRIGHT: (C)1993,JPO&Japio

Cooled Cascaded Frequency Multipliers at 1 THz

Abstract: It has been shown by theoretical calculations that the required all-solid-state local oscillator power for a Schottky diode mixer at 1 THz can be obtained by cooling a Schottky varactor frequency multiplier chain. The first reason for the higher output power by cooling is the decreased series resistance of the varactor, which increases the efficiency of the Schottky varactor frequency multiplier by 1-2 dB. The second and more important reason for the higher output power at submillimeter wavelengths is the increased maximum current of the Schottky varactor by cooling, which makes it possible to pump the junction capacitance more effectively. This is especially important for the last stage multiplier at 1 THz, when the optimum peak current needed to pump the capacitance is much higher than the maximum current of the varactor at the temperature of 300 K. The theoretical maximum output power at 1 THz is calculated to increase by about 8 dB from 50 ?W to 300 ?W, when the multiplier chain is cooled passively to the temperature of 150 K, for example in a satellite.

Semiconductor junction capacitance element with breakdown voltage protection

Abstract: An semiconductor junction capacitance element equipped with the function of preventing electrostatic breakdown is disclosed in which a main PN junction adapted to serve as variable capacitance diode is defined in an epitaxial layer of a first conductivity type. A diffusion layer of the first conductivity type is provided in the epitaxial layer at a position spaced apart from a lateral PN junction which is exposed at major surface of the epitaxial layer so that the breakdown voltage of the lateral PN junction is set up to be lower than the breakdown voltage of the main PN junction by virtue of the provision of the diffusion layer.

Slot antenna SIS mixers for submillimeter wavelengths

Abstract: We are developing improved versions of a slot antenna SIS mixer which we have previously described. The initial work demonstrated a double sideband noise temperature of 420 K for a 500 GHz quasi-optical SIS mixer employing a twin-slot antenna on a quartz dielectric substrate. A quartz hyperhemispherical lens is used to focus the incoming radiation onto the twin-slot antenna. The advantages of a twin-slot antenna include a low impedance (35 omega) and a clean, symmetric beam pattern into the dielectric with a 70 percent efficiency. In our original mixer, the radiation was coupled from the two slot antennas onto superconducting microstrip lines which fed the SIS junction. By performing an impedance transformation using tapered lines and by feeding the radiation from the two slots to the junction in parallel, the effective (real) impedance seen by the junction was reduced to just 4 omega. This very low impedance allowed a junction area of 2.3 sq micron to be used at 500 GHz, which was manufactured using optical lithography. However, no attempt was made to tune out the junction capacitance. We estimate that this capacitance reduces the impedance coupling efficiency to eta(sub Z) approx. equals 0.23, for our junction with omega R(sub N) C = 5.3 at 500 GHz. The recent development of techniques using electron-beam lithography to manufacture junctions with very small areas (approx. equals 0.1 sq microns) now allows considerably more flexibility in the design of SIS mixer circuits. We have redesigned the slot-antenna mixer to take advantage of this possibility. In particular, we have included a novel circuit which allows the junction capacitance to be tune out over a broad bandwidth. For instance, mixers designed for 800 GHz using NbN/MgO/NbN junctions with realistic parameters achieve a 3 dB impedance bandwidth of nearly 400 GHz. Furthermore, our circuit uses only short lengths of microstrip and should be less sensitive to RF losses than other designs. The improved impedance match should give a large reduction in noise temperature as compared to our previous mixer. The new devices are currently under fabrication. Further details of the design and any available experimental results are discussed.

Monolithic microwave integrated voltage controlled oscillator circuit

Abstract: PURPOSE:To expand the oscillating frequency range without increased modulation sensitivity by varying a reference bias voltage so as to revise an oscillating frequency due to a change in the junction capacitance of a 2nd varactor. CONSTITUTION:A reference bias voltage fed to a cathode terminal of oscillation frequency adjustment varactors 1-6, 1-7 externally via a terminal 1-19 and high frequency blocking resistors 1-14, 1-16 is varied with an operating frequency band. Thus, the oscillating frequency is jumped by a change in the reverse bias state of 2nd varactors 1-23, 1-24 in addition, that is, a change in the junction capacitance. Thus, the expansion of the variable range in the oscillating frequency is executed without increasing the modulation sensitivity.

12.8-ps 1.0-mW charge-buffered active pull-down NTL circuit

Abstract: An NTL circuit with a charge-buffered active-pulldown emitter-follower stage is described. The circuit utilizes the diffusion capacitance of a charge-storage diode (CSD) as the coupling element between the common-emitter node of the switching transistors and the base of an active-pull-down n-p-n transistor to generate a large dynamic current for the pull-down transistor and to provide a speedup effect on the switching logic stage. Implemented in a 0.8- mu m double-poly trench-isolated self-aligned bipolar process, unloaded gate delays of 12.8 ps/1.0 mW, 15.4 ps/0.71 mW, and 18.0 ps/0.53 mW have been achieved. >

Method for measuring and extracting junction capacitance of transistor

Abstract: PURPOSE: To evaluate junction capacitance in a high frequency area and to automate, simplify and facilitate a system for measuring and extracting transistor model parameters by extracting the junction capacitance parameters of a transistor from data on the measurements of an S-parameter CONSTITUTION: The base terminal B and collector terminal C of a transistor 9 to be tested are connected to the respective ports P 1 , P 2 of an S-parameter measuring instrument through respective transistors 13 Because a baseemitter junction BE and a base-collector junction BC are evaluated in a reversely biased state, VCE=0V and VBE<0V and the bias dependencies of the baseemitter junction BE, the base-collector junction BC and the collectorsubstrate junction CS are measured while the values of two voltage sources 16, 17 are varied After a bias voltage has been set, an S-parameter is measured by the S- parameter measuring instrument and the S-parameter measured is converted into a Z-parameter and the true portion of the Z-parameter is set to zero and is converted into a Y-parameter so as to obtain the capacitance of each junction COPYRIGHT: (C)1993,JPO&Japio

Field effect transistor and method of fabricating

Abstract: A junction field effect transistor, specifically a static induction transistor. The N-type source regions are formed as two zones. First, relatively lightly doped first zones are formed by ion-implanting doping material relatively deeply into the semiconductor material. Then relatively heavily doped second zones are formed by ion-implanting doping material to a relatively shallow depth within the first zones to leave portions of the first zones interposed between the second zones and the remainder of the semiconductor material. The resulting devices exhibit reduced gate-drain junction capacitance at low drain bias voltages thereby improving device capacitance linearity.

Differential amplifier circuit

Abstract: PURPOSE:To easily attain broad band processing with accuracy without increasing a current consumption of the circuit by providing a circuit giving a same junction capacitance as that being a parasitic capacitance in existence in a load resistor and generating a current in phase with a signal current generated in the differential amplifier circuit on the differential amplifier circuit. CONSTITUTION:An in-phase voltage to an input voltage 10 is generated in a load resistor 3 by the input voltage 10 inputted to a transistor(TR) 1 and an inverting voltage is generated across a load resistor 4. An in-phase voltage to the input voltage 10 is generated to an emitter of a TR 14 by the voltages, an inverting voltage is caused to an emitter of the TR 15 to generate an in- phase current i4 to a current i1 flowing to a collector of a TR 2 and diodes 16,17. Then the substantial signal current i1 is entirely equal to a current i2 flowing to the load resistor 3 by adjusting the current i4 flowing to the diodes 16,17 so as to make the current i4 coincident with the current i3 flowing to a parasitic capacitance 5.

Collector–Base Junction Capacitance of Advanced Bipolar Transistors Operating at Avalanche Breakdown

Abstract: Modeling of the collector–base junction capacitance of the advanced bipolar transistors operating at avalanche breakdown is developed. The comprehensive junction capacitance model accounts for high current and high field effects at the collector–base junction. The impact ionization generates tremendous amount of free carriers in the collector–base space-charge region which increases the collector–base junction capacitance at the avalanche breakdown regime. The present collector–base junction capacitance is useful for device and circuit design under avalanche breakdown prior to the actual fabrication of the circuit.