Showing papers on "Drain-induced barrier lowering published in 2018"

Improved Subthreshold Swing and Short Channel Effect in FDSOI n-Channel Negative Capacitance Field Effect Transistors

Abstract: Negative capacitance (NC) FETs with channel lengths from 30 nm to $50~\mu \text{m}$ , gated with ferroelectric hafnium zirconium oxide are fabricated on fully depleted silicon-on-insulator (FDSOI) substrates. Enhanced capacitance due to NC, hysteresis-free operation, and improved subthreshold slope are observed. The NC effect leads to enhancement of drain current for small voltage operation. In addition, improved short channel performance is demonstrated owing to the reverse drain induced barrier lowering characteristics of the NC operation.

Negative Capacitance, n-Channel, Si FinFETs: Bi-directional Sub-60 mV/dec, Negative DIBL, Negative Differential Resistance and Improved Short Channel Effect

Abstract: We report on negative capacitance (NC) FinFETs with ferroelectric Hf 0.5 Zr 0.5 O 2 (HZO) as gate dielectric on fully depleted silicon on insulator (FDSOI) substrate with various channel length (L CH ) of 450 nm to 30 nm and multiple fin widths (W FIN ) of 200 nm to 30 nm. We demonstrate all signature characteristics expected from NCFET: nearly hysteresis free operation (~3 mV), D and to the best of our knowledge, for the first time in Si MOSFETs, negative Drain Induced Barrier Lowering (DIBL) and Negative Differential Resistance (NDR). Remarkably, we observe significant improvement in the short channel effect compared to control FinFETs: both SS and DIBL are substantially lower for the NCFET for the same L ch /W Fin ratio. Importantly, these benefits become increasingly larger for shorter channel lengths.

A Closed Form Analytical Model of Back-Gated 2-D Semiconductor Negative Capacitance Field Effect Transistors

Abstract: Steep slope ( $SS mV/dec at room temperature) negative capacitance (NC) FETs, based on the 2-D transition metal dichalcogenide semiconductor channel materials, may have a promising future in low-power electronics because of their high on-state current and very high on/off ratio. In this paper, we develop an analytically compact drain current model for long-channel back-gated 2-D NC-FETs by solving the classical drift-diffusion equations. The equations describe the transition from depletion to accumulation regimes of operation as a continuous function of gate/drain voltages. The continuity ensures time-efficient simulation of large systems. Several key features of the model are verified by comparing with the experimental data. Specifically, the negative drain induced barrier lowering effect and negative differential resistance effect predicted by the model are successfully observed in our experiments.

Surface Potential Modeling of Graded-Channel Gate-Stack (GCGS) High-K Dielectric Dual-Material Double-Gate (DMDG) MOSFET and Analog/RF Performance Study

Abstract: In each complementary metal-oxide-semiconductor (CMOS) technology generation, design of new device architectures at nanoscale regime becomes quite challenging task due to increased short channel effects (SCEs) and leakage current. A double-gate (DG) MOSFET is an alternative structure. To enhance the performance of DG MOSFET, gate stack (GS) and dual-material gate (DMG) with graded-channel (GC) concepts are amalgamated. Analytical surface potential modeling of GCGS DMDG MOSFET has been done by solving the two-dimensional (2D) Poisson’s equation with suitable boundary conditions. The surface potential profile of GCGS DMDG MOSFET shows a step variation at the interface of two materials. The electrical parameters drain induced barrier lowering (DIBL), sub-threshold swing (SS) and on-current to off-current $\left (\frac {I_{on}}{I_{off}}\right )$ ratio reveals that, DMDG shows a better performance over single-material (SM) DG MOSFET with all (Si3N4, HfO2 and Ta2O5) GS high-k dielectric configurations. An enhanced performance in GCGS DMDG is due to the fact of increased average carrier velocity, reduced drain field effect and leakage current. Further, analog/RF performance parameters such as transconductance (gm), transconductance generation factor (TGF), cut-off frequency (fT), transconductance generation frequency product (TGFP), gain frequency product (GFP) and gain transconductance frequency product (GTFP) are extracted and compared for both SMDG and DMDG MOSFET with HfO2 GS configuration. The efficacy of analytically modeled results is compared with numerically simulated results obtained from 2D ATLAS device simulator.

A Two-Dimensional (2D) Analytical Modeling and Improved Short Channel Performance of Graded-Channel Gate-Stack (GCGS) Dual-Material Double-Gate (DMDG) MOSFET

Abstract: A Double-gate (DG) metal-oxide-semiconductor field effect transistor (MOSFET) is emerging device architecture in sub-nanometer regime. The performance of DG MOSFET can be ameliorated by gate and channel engineering. The concept of graded-channel gate-stack (GCGS) and dual-material (DM) are incorporated in DG MOSFET. A two-dimensional (2D) analytical surface potential model for GCGS DMDG MOSFET is developed based on the solution of Poisson’s equations with appropriate boundary conditions. It has been found that analytically modeled data is in good degree of agreement with numerically simulated data. The combination of both DM and GC concept introduces a step variation in potential profile at the junction of both materials in channel region and ameliorates the short channel effects (SCEs). A suppressed subthreshold swing (SS) and drain induced barrier lowering (DIBL) has been observed in the device due to an elevated average velocity of carrier and reduced drain field effect by the use of DM and GC with GS. Further, analog/RF characteristics such as transconductance generation factor (TGF), cut-off frequency (fT) and transconductance frequency product (TFP) have been examined with different GS high-k dielectrics. The numerically simulated data has been extracted using 2D ATLAS device simulator.

Performance Enhancement of FinFET Devices with Gate-Stack (GS) High-K Dielectrics for Nanoscale Applications

Abstract: The Fin shaped Field Effect Transistors (FinFETs), are the front runner of the current sub-nanometer technology node. The semiconductor industry adopts it in high-performance (HP) and low-power (LP) applications due to greater electrostatic control and better scalability. This paper explores the numerically simulation based comparison of bulk and silicon-on-insulator (SOI) technology double gate (DG), triple gate (TG) FinFETs. The essential processing steps required to create the GS high-k dielectric bulk and SOI FinFETs are demonstrated. The electrical performance parameters of the device such as Ion/Ioff ratio, subthreshold swing (SS), and drain induced barrier lowering (DIBL) are extracted. Based on the three-dimensional (3D) ATLASTM simulation results, TG FinFET shows an ameliorated performance over DG in bulk and SOI technology as well. In order to control the short channel effects (SCEs), gate-stack (GS) high-k dielectrics are introduced with fixed thickness interfacial-layer (IL) and high-k dielectric material in between the gate material and semiconductor. The GS high-k dielectrics suppress the SCEs to large extent in both devices and technologies. The GS SOI FinFETs demonstrates the improved performance over the bulk counterpart and TG FinFET is the best among them. Further, the similar kind of investigation has been carried out for Tfin variations. These devices reveal the excellent control of SCEs when the fin is narrow. The ratio of SOI and bulk TG FinFET Ion/Ioff ratio with Tfin variations provide evidence that, the SOI based devices are competent for HP and LP applications.

Ferroelectric HfZrO x FETs on SOI Substrate With Reverse-DIBL (Drain-Induced Barrier Lowering) and NDR (Negative Differential Resistance)

Abstract: Ferroelectric-Hf1−xZrxO2 FETs on silicon on insulator (SOI) are modeled and demonstrated with improvement on subthreshold swing (SS) and hysteresis ( $V_{T}$ -shift), which is based on the capacitance matching concept The minimum reverse SS = 45 mV/dec and 52 mV/dec are obtained experimentally for SOI and bulk-Si, respectively The steep SS range (<60 mV/dec) is extended from ~25 (bulk-Si) decades to ~35 decades SOI Reverse-drain-induced barrier lowering and negative differential resistance are confirmed at subthreshold region and weak inversion region, respectively

Insinhts on the DC Characterization of Ferroelectric Field-Effect-Transistors

Abstract: In this work, we report on the fabrication, characterization, and modeling of ferroelectric field-effect- transistors (FeFET). We demonstrate that polarization switching within ordinary 1T ferroelectric memory devices under specific conditions results in the measurement of subthreshold slopes $ , near-zero hysteresis, negative drain induced barrier lowering (N-DIBL), and negative differential resistance (NDR) (Fig. 1). The polarization switching origin is identified by a strong dependence on the magnitude of the gate voltage, where below the critical gate voltage required to switch polarization, $\mathrm{SS} , near-zero hysteresis, and negative DIBL cannot be observed. Further, we identify the source of NDR in the output characteristics to result from polarization switching near the drain of the FeFET at 10w $\mathrm{V}_{\mathrm{GS}}$ and high $\mathrm{V}_{\mathrm{DS}}$ . The NDR can be reproduced by a simple analytical model where two VT are present within the FeFET channel due to a non-uniform distribution of the polarization charge along the channel length. The intent of this work is to disambiguate and draw distinction between the effects of polarization switching in FeFET memory devices from that of negative capacitance as shown in Kwon et. al. [1], where a physically thicker oxide shows all the electric nronerties of a nhvsicallv thinner dielectric.

Impact of High-k Spacer on Device Performance of Nanoscale Underlap Fully Depleted SOI MOSFET

Abstract: The fully depleted Silicon-On-Insulator MOSFETs (FD-SOI) have shown high immunity to short channel effects compared to conventional bulk MOSFETs. The inclusion of gate underlap in SOI structure further improves the device performance in nanoscale regime by reducing drain induced barrier lowering and leakage current (IOFF). However, the gate underlap also results in reduced ON current (ION) due to increased effective channel length. The use of high-k material as a spacer region helps to achieve the higher ION but at the cost of increased effective gate capacitance (CGG) which degrades the device performance. Thus, the impact of high-k spacer on the performance of underlap SOI MOSFET (underlap-SOI) is studied in this paper. To fulfil this objective, we have analyzed the performance parameters such as CGG, ION, IOFF, ION/IOFF ratio and intrinsic transistor delay (CV/I) with respect to the variation of device parameters. Various dielectric materials are compared to optimize the ION/IOFF ratio and CV/I for nanoscale underlap-SOI device. Results suggest that the HfO2 of 10nm length is optimum value to enhance device performance. Further, the higher underlap length is needed to offset the exponential increase in IOFF especially below 20nm gate length.

Drain-Induced Barrier Lowering in Oxide Semiconductor Thin-Film Transistors With Asymmetrical Local Density of States

Abstract: Asymmetrical electrical properties induced by local acceptor-like defect states in oxide semiconductor thin-film transistors are investigated. In addition, we report on the origin of asymmetrical transport characteristics depending on the drain voltage level. In particular, we observe that these asymmetrical properties depend strongly on this level. Numerical calculations demonstrate that potential barrier lowering in the local area occurs at the drain electrode’s edge.

Performance Optimization of Broadwell-Y Shaped Transistor Using Artificial Neural Network and Moth-Flame Optimization Technique

Abstract: FinFETs are the emerging 3D-transistor structures due to strong electrostatic control of active channel by gate from more than one side which was not possible in conventional transistor. FinFET structures with rectangular and trapezoidal shape have been excessively analyzed in literature. In this work, FinFET with Broadwell-Y shape proposed by Intel, has been designed and simulated in Technology Computer Aided Design (TCAD). The performance of the designed device was optimized using Moth Flame Optimization (MFO) after the network was trained through Artificial Neural Network (ANN). Results obtained from MATLAB were in close agreement with those obtained from TCAD simulations. Output parameters like leakage current (IOFF) of 2.407e-12, On-Off current ratio (ION/IOFF) of 4.5e06, Subthreshold Swing (SS) of 65.4mV/dec and Drain Induced Barrier Lowering (DIBL) of 37.9mV/V were obtained after optimization. Short channel effects are improved for 20nm gate length as SS is close to ideal value 60mV/dec and DIBL is below 100mV/V which makes this designed structure a good option for nanoscale applications.

A threshold voltage and drain current model for symmetric dual-gate amorphous InGaZnO thin film transistors

Abstract: Based on the drift-diffusion theory, a simple threshold voltage and drain current model for symmetric dual-gate (DG) amorphous InGaZnO (a-IGZO) thin film transistors (TFTs) is developed. In the subthreshold region, most of the free electrons are captured by trap states in the bandgap of a-IGZO, thus the ionized trap states are the main contributor to the diffusion component of device drain current. Whereas in the above-threshold region, most of the trap states are ionized, and free electrons increase dramatically with gate voltage, which in turn become the main source of the drift component of device drain current. Therefore, threshold voltage of DG a-IGZO TFTs is defined as the gate voltage where the diffusion component of drain current equals the drift one, which can be determined with physical parameters of a-IGZO. The developed threshold voltage model is proved to be consistent with trap-limited conduction mechanism prevailing in a-IGZO, with the effect of drain bias being also taken into account. The gate overdrive voltage-dependent mobility is well modeled by the derived threshold voltage, and comparisons of the obtained drain current with experiment data show good verification of our model.

An Improved Large Signal Model for 0.1 μm AlGaN/GaN High Electron Mobility Transistors (HEMTs) Process and Its Applications in Practical Monolithic Microwave Integrated Circuit (MMIC) Design in W band.

Abstract: An improved empirical large signal model for 0.1 µm AlGaN/GaN high electron mobility transistor (HEMT) process is proposed in this paper. The short channel effect including the drain induced barrier lowering (DIBL) effect and channel length modulation has been considered for the accurate description of DC characteristics. In-house AlGaN/GaN HEMTs with a gate-length of 0.1 μm and different dimensions have been employed to validate the accuracy of the large signal model. Good agreement has been achieved between the simulated and measured S parameters, I-V characteristics and large signal performance at 28 GHz. Furthermore, a monolithic microwave integrated circuit (MMIC) power amplifier from 92 GHz to 96 GHz has been designed for validation of the proposed model. Results show that the improved large signal model can be used up to W band.

Evaluation of a 100-nm Gate Length E-Mode InAs High Electron Mobility Transistor With Ti/Pt/Au Ohmic Contacts and Mesa Sidewall Channel Etch for High-Speed and Low-Power Logic Applications

Abstract: In this paper, a 100-nm gate length InAs high electron mobility transistor (HEMT) with non-alloyed Ti/Pt/Au ohmic contacts and mesa sidewall channel etch was investigated for high-speed and low-power logic applications. The device exhibited a low subthreshold swing (SS) of 63.3 mV/decade, a drain induced barrier lowering value of 23.3 mV/V, an ION/IOFF ratio of 1.34 $\times$ 104, a Gm,max/SS ratio of 27.6, a current gain cut-off frequency of 439 GHz with a gate delay time of 0.36 ps, and an off-state gate leakage current of less than 1.6 $\times 10^{-5}$ A/mm at VDS = 0.5 V. These results demonstrated that the presence of non-annealed ohmic contacts with mesa sidewall etch process allowed the fabrication of InAs HEMTs with excellent electrical characteristics for high-speed and low-power logic applications.

Suppression of drain-induced barrier lowering by double-recess overlapped gate structure in normally-off AlGaN-GaN MOSFETs

Abstract: We investigated drain-induced barrier lowering (DIBL) in normally-off AlGaN-GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with a double-recess overlapped gate structure. It is found that the double-recess overlapped gate structure can suppress DIBL; the threshold voltage is constant without lowering for high drain-source voltages, and sub-threshold characteristics remains excellent. We elucidate the mechanism of the DIBL suppression by considering a local potential in the MOSFETs. In addition, it is also found that the double-recess overlapped gate structure is beneficial for current collapse suppression.We investigated drain-induced barrier lowering (DIBL) in normally-off AlGaN-GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with a double-recess overlapped gate structure. It is found that the double-recess overlapped gate structure can suppress DIBL; the threshold voltage is constant without lowering for high drain-source voltages, and sub-threshold characteristics remains excellent. We elucidate the mechanism of the DIBL suppression by considering a local potential in the MOSFETs. In addition, it is also found that the double-recess overlapped gate structure is beneficial for current collapse suppression.

Modified Schottky Barrier CNTFET with lightly doped drain

Abstract: For the first time, a modified Schottky barrier carbon nanotube field-effect transistor (SB-CNTFET) with lightly doped drain (LDD) has been proposed. The newly designed CNTFET benefits from the advantages of both SB in source and the lightly doped ohmic drain contact. Simulations are based on two-dimensional non-equilibrium Green's function solved self-consistently with Poisson's equation. To get to an improved electrical characteristic, comparisons have been made among four CNTFET structures which are conventional SB-CNTFETs, triple LDD-CNTFET (TLDD-CNTFET), double LDD-CNTFET and Schottky source and ohmic drain CNTFET. The results show that the TLDD-CNTFET design decreases the leakage current significantly and increases on–off-current ratio as well as the cut-off frequency. It is also demonstrated that TLDD-CNTFET structure possesses three perceivable steps in the potential profile of the channel, which leads to additional lateral electric field peaks inside the channel and thus improve the immunity against short-channel effects. The important parameters such as transconductance, on–off ratio, subthreshold swing, cut-off frequency, delay and drain-induced barrier lowering of the CNTFETs have been calculated and discussed. Results show that by using lightly doped regions in the drain of SB-CNTFETs, the dc and ac characteristics have been considerably improved compared with the conventional SB-CNTFET.

High Performance Low Leakage Pocket Si x Ge 1-x Junction-Less Single-Gate Tunnel FET for 10 nm Technology

Abstract: This paper presents a low leakage pocket Si x -Ge 1-x , junction-less tunnel FET suitable under low voltage region. Junction-less single-gate TFET expolits the steep subthreshold characteristics of tunnel FET as well as the high on current due to junction-less behaviour. Pocket region(5nm) of narrow band gap material Si x -Ge 1-x , decreases tunneling distance and improves the $\mathrm{I}_{\mathrm{o}\mathrm{n}}/\mathrm{I}_{\mathrm{o}\mathrm{f}\mathrm{f}}$ ratio. The proposed pocket Junction-less TFET has been designed on 2D/3D Visual TCAD device simulator for 10nm technology to optimize subthreshold parameters such as subthreshold slope, drain induced barrier lowering and leakage current. Such low leakage, low power pocket Junction-less SGTFET is suitable for analog and digital applications.

Comparison of Electrical Characteristics of 28 Nm Bulk MOSFET and FDSOI MOSFET

Abstract: In this paper, 28 nm Bulk MOSFET and Fully Depleted Silicon On Insulator (FDSOI) MOSFET are designed. FDSOI is three layered device as it has Buried Oxide layer (BOX)between channel and substrate. The computer simulations of the Bulk MOSFET and FDSOI MOSFET device designs are performed on COGENDA Visual TCAD tool. The comparison of both the devices has been done on the basis of threshold voltage, current in ON state, current in OFF state, Current ratio (ON/OFF), Transconductance (g m ), Figure of Merit (FOM), Electrostatic Integrity (EI)and Drain Induced Barrier Lowering (DIBL). It is observed that FDSOI MOSFET has better current ratio (ON/OFF)as compared to Bulk MOSFET.

GaAs SOI FinFET: impact of gate dielectric on electrical parameters and application as digital inverter

Abstract: In this paper, a GaAs SOI (silicon on insulator) FinFET is proposed. A comparative study between proposed GaAs FinFET and conventional Si FinFET is presented. The effects of dielectric constant (k) of gate dielectric material on electrical parameters like channel potential, drain current, and Ion/Ioff have been reported. Results show that as k raises, both Ion/Ioff and channel potential increases. Again the impact of k on short channel effects (SCEs) has been investigated. TCAD results show that as k increases subthreshold swing (SS) improves, drain induced barrier lowering (DIBL) degrades, and VT roll off occur. The impacts of k on gate capacitance (CGG) and intrinsic delay (τ) have been presented and they increases as k increases. A digital CMOS inverter is implemented through proposed FinFET and the effect of k on its delay parameter is estimated. Results shows that average delay increase as k increases.

Channel Engineered Cylindrical Double Gate All Around FET For Low Power VLSI Applications

Abstract: A specific channel engineering over a cylindrical double gate all around FET (CDGAA FET) is proposed in this work. The engineering is to stack 3 layers of diversely doped silicon in channel region in order to attain a much better carrier concentration in all states of FET operation. This modified FET is termed as channel engineered cylindrical double gate all around FET (CE-CDGAA FET). The simulation results reveal that this modification provides reduced off current (Ioff), greatly enhanced on current (Ion) and boosts the on-off current ratio (Ion/Ioff). The proposed modification also lowers the drain induced barrier lowering (DIBL) and subthreshold swing (SS) compared to CDGAA FET. This evolution allows downscaling a FET up to 3nm channel length with acceptable performance in many of its performance parameters, marking its applicability in VLSI and low power FET applications. A comparative study between CE-CDGAA FET and CDGAA FET is also presented in this work.

Performance Enhancement of Multi-Gate MOSFETs Using Gate Dielectric Engineering

Abstract: Short channel effects (SCEs) are major roadblocks for Bulk MOSFETs to scale down into nanometer regime. Multi-gate (Double-Gate (DG), Triple-gate (TG) Gate all around (GAA)) structures are the best alternatives to tackle the SCEs. This paper initially compares multi-gate devices along with single gate with respect to different gate oxide thickness. To improve the performance of these devices, gate-stack (stacking of SiO2 and HfO2 layers) configuration is introduced and compared their electrical characteristics such as ION/IOFF ratio, Subthreshold swing, and drain induced barrier lowering (DIBL). Further, gate-engineered dielectric layer comprising of one dielectric (HfO2) in half-gate length and another dielectric (SiO2) in the other half of gate length are used side by side with identical thickness. At all stages, GAA structure exhibits better performance over the others. In order to estimate the devices performances at circuit level, a resistive load based inverter circuit has been simulated with gate-engineered multi-gate structures and found that GAA based inverter gives less delay time in comparison with others.

Field effect transistor and manufacturing method therefor

Abstract: Provided are a field effect transistor and a manufacturing method therefor, which relate to the technical field of electronics. The field effect transistor comprises a substrate layer (1), a channel layer (2), a source electrode (3), a drain electrode (4), a dielectric layer (5) and a gate electrode (6). The channel layer (2) covers an upper surface of the substrate layer (1), and the channel layer (2) comprises a first region (21) and a second region (22), the first region (21) and the second region (22) both comprising at least one via hole therein, each via hole being used for penetrating through the channel layer (2) so as to expose the substrate layer (1), and the shape of each via hole being fractal, wherein a fractal pattern is determined and obtained based on a specified pattern, and the ratio between the perimeters of the fractal pattern and the specified pattern is greater than the ratio between areas of the fractal pattern and the specified pattern. The source electrode (3) is located above the first region (21) in the channel layer (2), and the source electrode (3) and the substrate layer (1) are directly connected at at least one via hole position of the first region (21). The drain electrode (4) is located above the second region (22) in the channel layer (2), and the drain electrode (4) and the substrate layer (1) are directly connected at at least one via hole position of the second region (22). This field effect transistor cannot generate other additional overlarge resistance, while effectively reducing the contact resistance between the source electrode, the drain electrode and the channel layer, thereby being capable of ensuring the effectiveness of the field effect of the field effect transistor.

Effect of Gate-lap and Oxide Material at 10-nm FinFET Device Performance

Abstract: FinFETs have displayed superior electrical behavior as the promising substitute to the planar devices with improved electrostatic control, though FinFETs have been encountered with key obstacles of device scaling for better performance. In this research work, a FinFET structure has been simulated at 10-nm technology node. The electrical performance of the device has been investigated at various gatelap lengths and with utilizing high-k gate insulating material in the device structure for understanding their influence on the device performance. Low subthreshold$\sim 76.33$ mV/decade is obtained at gate-lap distance 0.5 nm. There have been obtained improvements in the ON to OFF current Ratio (I ON /I OFF ), Subthreshold swing (SS), and Drain Induced Barrier Lowering (DIBL) when the gate-lap length is varied. The results showed significant role of gate-lap length variation in the device parametrs. These research results are useful in guiding for scaling and design improvements of multi-gate device structures.

Perspective of Buried Oxide Thickness Variation on Triple Metal-Gate (TMG) Recessed-S/D FD-SOI MOSFET

Abstract: Recently, Fully-Depleted Silicon on Insulator (FD-SOI) MOSFETs have been accepted as a favourable technology beyond nanometer nodes, and the technique of Recessed-Source/Drain (Re-S/D) has made it more immune in regards of various performance factors. However, the proper selection of Buried-Oxide (BOX) thickness is one of the major challenges in the design of FD-SOI based MOS devices in order to suppress the drain electric penetrations across the BOX interface efficiently. In this work, the effect of BOX thickness on the performance of TMG Re-S/D FD-SOI MOSFET has been presented at 60 nm gate length. The perspective of BOX thickness variation has been analysed on the basis of its surface potential profile and the extraction of the threshold voltage by performing two-dimensional numerical simulations. Moreover, to verify the short channel immunity, the impact of gate length scaling has also been discussed. It is found that the device attains two step-up potential profile with suppressed short channel effects. The outcomes reveal that the Drain Induced Barrier Lowering (DIBL) values are lower among conventional SOI MOSFETs. The device has been designed and simulated by using 2D numerical ATLAS Silvaco TCAD simulator.

Study of Circuits Based on SOI-vertical Gate-All-Around FET

Abstract: The device performance of silicon-on-insulator vertical gate all around field effect transistor (SOI-VGAAFET) with three channels and optimal gate length is presented. The electrical parameters of the SOI-VGAAFET are compared with the bulk VGAAFET. SOI-VGAAFET exhibits low leakage current, good sub-threshold slope and low drain induced barrier lowering compared to the bulk VGAAFET device. The performance of analog and digital circuits based on SOI-VGAAFET are studied using three-dimensional mixed-mode device simulations. The results indicate that SOI-VGAAFET with optimal gate length is a suitable device in analog and mixed-signal integrated circuit applications at low feature-length and low supply voltage.

Study of Linearity Performances of Junction-less Triple-Material Cylindrical Surrounding Gate MOSFET

Abstract: In the proposed work, the study and thorough analysis of JLTMCSG MOSFET has been done. Its comparison with JLDMCSG MOSFET also being done based on different parameter variations like linearity study taking into account various suitable linearity metrics such as gm1, gm2, gm3,1-dB compression point, VIP2, VIP3 and IIP3. The analysis suggests that if designed properly JLTMCSG MOSFET will have superior linearity performance. At the same time distortion can be reduced due to lowered drain induced barrier lowering. It has a higher and more uniformity produced in the electric field which is suitable applications in microwave applications and RF communication and low noise amplifiers.

A Multi Vt Approach for Silicon Nanotube FET with Halo Implantation for Improved DIBL

Abstract: An effective way to get multiple threshold voltage modulation scheme in Silicon nano tube FET combining unbalanced halo doping is proposed and verified by 3D TCAD Simulator. The typical choice to accomplish multiple threshold voltages is by choosing the appropriate gate work-function for each device. But this results in higher process complexity. In this report we demonstrate the multiple V t solution for Si-NTFET at 14 nm technology node. Using HALO at source side, the simulated DIBL (Drain induced Barrier Lowering)characteristics shows notable improvement.

Sub-nano Regime DG-MOSFETs

Abstract: The significance of device performance of Gallium Nitride based double gate metal-oxide- semiconductor field-effect-transistor has been executed. The simulations were done by Silvaco Atlas simulation software with focusing on non-equilibrium green function (NEGF). Multiple gate length (L G =9.1 nm) was observed to distinguish the transfer characteristics curve. The other concentration was observed for device ON-State Current (I ON ), OFF-State Current (I OFF ), Drain Induced Barrier Lowering (DIBL), Sub Threshold Slope (SS) and Electric Field (E F ). Keywords: Transfer characteristics curve, Double gate MOSFETs, I ON , DIBL, SS Cite this Article Md. Rabiul Islam, Md. Rokib Hasan, Md. Abdul Mannan et al . Sub-nano Regime DG-MOSFETs. Journal of Semiconductor Devices and Circuits . 2018; 5(3): 1–6p.

Sub-Threshold Drain Current Model of Shell-Core Architecture Double Gate JunctionLess Transistor

Abstract: Sub-threshold model for advanced shell doped Double Gate Junctionless transistor has been presented in this work. Electrical parameters such as potential, threshold voltage Vth, leakage current I off , sub-threshold slopes SS and Drain Induced Barrier Lowering DIBL are evaluated analytically and compared with the results extracted from ATLAS TCAD software. Different configurations of shell doping have been used in this work such as: high-low-high, low-high-low, low-low-high and uniform. Obtained results shows that high-low-high doping profile of DG-JL transistor suppresses the leakage current more efficiently and also provide good sub-threshold slope and DIBL compared to uniform and other doping profiles. In shell doped DG-JL transistor, additional tuning parameter is present (i.e. the thickness of individual doping layer)which further helps in optimizing the device design for sub-20nm circuits' applications.