Showing papers on "Fault indicator published in 1996"

A new approach to on-line turn fault detection in AC motors

Abstract: Turn fault detection is based on the principal that symmetrical (unfaulted) motors powered by symmetrical multiphase voltage sources will have no negative sequence currents flowing in the leads. A turn-to-turn fault will break that symmetry and give rise to a negative sequence current which may then be used as a measure of fault severity or to initiate protective action such as a circuit breaker trip. A new way of looking at the effects of turn faults has been developed that improves sensitivity and speed while reducing the probability of misdetection, taking into account voltage balance, load or voltage variation and instrument errors. The method has been implemented on a PC and tested, in real time, on a specially prepared small motor. Reliable detection of one shorted turn out of 648 turns per phase (in a Y connected motor) was demonstrated with the fault indicator becoming fully developed in two cycles of line frequency after initiation of the fault.

Unsynchronized two-terminal fault location estimation

Abstract: A technique for power system fault location estimation which uses data from both ends of a transmission line and which does not require the data to be synchronized is described. The technique fully utilizes the advantages of digital technology and numerical relaying which are available today and can easily be applied for offline analysis. This technique allows for accurate estimation of the fault location irrespective of the fault type, fault resistance, load currents, and source impedances. Use of two-terminal data allows the algorithm to eliminate previous assumptions in fault location estimation, thus increasing the accuracy of the estimate. The described scheme does not require real-time communications, only offline post-fault analysis. The paper also presents fault analysis techniques utilizing the additional communicated information.

Network fault correlation

Abstract: A method and apparatus for correlating faults in a networking system. A database of fault rules is maintained along with and associated probable causes, and possible solutions for determining the occurrence of faults defined by the fault rules. The fault rules include a fault identifier, an occurrence threshold specifying a minimum number of occurrences of fault events in the networking system in order to identify the fault, and a time threshold in which the occurrences of the fault events must occur in order to correlate the fault. Occurrences of fault events in the networking system are detected and correlated by determining matched fault rules which match the fault events and generating a fault report upon determining that a number of occurrences for the matched fault rules within the time threshold is greater than or equal to the occurrence threshold for the matched fault rules.

System and method for performing real time data acquisition, process modeling and fault detection of wafer fabrication processes

Abstract: A system and method for detecting faults in wafer fabrication process tools by acquiring real-time process parameter signal data samples used to model the process performed by the process tool. The system includes a computer system including a DAQ device, which acquires the data samples, and a fault detector program which employs a process model program to analyze the data samples for the purpose of detecting faults. The model uses data samples in a reference database acquired from previous known good runs of the process tool. The fault detector notifies a process tool operator of any faults which occur thus potentially avoiding wafer scrap and potentially improving mean time between failures. The fault detector also receives notification of the occurrence of process events from the process tool, such as the start or end of processing a wafer, which the fault detector uses to start and stop the data acquisition, respectively. The fault detector also receives notification of the occurrence of a new process recipe and uses the recipe information to select the appropriate model for modeling the data samples. The fault detector employs a standard data exchange interface, such as DDE, between the fault detector and the model, thus facilitating modular selection of models best suited to the particular fabrication process being modeled. Embodiments are contemplated which use a UPM model, a PCA model, or a neural network model.

Practical High Impedance Fault Detection for Distribution Feeders

Abstract: Distribution protection systems must balance dependability with security considerations to be practical. This is quite difficult for high-impedance faults. Only highly sensitive algorithms can achieve absolute dependability in detecting very low current faults. This high sensitivity results in a propensity for false tripping, creating a less secure, system and resulting in the potential for decreased service continuity and lower reliability. Researchers at Texas A&M University have balanced fault detection with fault discrimination, resulting in a practical combination of detection algorithms in a commercially viable system. This device has many "intelligent" features, including the ability to analyze and correlate numerous fault characteristics in real time, so that a correct determination of the status of the feeder can be made with a high probability of accuracy. This paper describes the use of multiple algorithms to detect various types of faults and the use of an expert decision maker to decipher incoming data, to determine the status and health of a distribution feeder. Requirements for a practical, secure high-impedance fault relay are also discussed. Finally, Texas A&M has licensed this technology to a commercial partner, which manufactures a device that detects high-impedance faults, in addition to performing numerous other monitoring and protection functions.

A gate-level simulation environment for alpha-particle-induced transient faults

Abstract: Mixed analog and digital mode simulators have been available for accurate /spl alpha/-particle-induced transient fault simulation. However, they are not fast enough to simulate a large number of transient faults on a relatively large circuit in a reasonable amount of time. In this paper, we describe a gate-level transient fault simulation environment which has been developed based on realistic fault models. Although the environment was developed for /spl alpha/-particle-induced transient faults, the methodology can be used for any transient fault which can be modeled as a transient pulse of some width. The simulation environment uses a gate level timing fault simulator as well as a zero-delay parallel fault simulator. The timing fault simulator uses logic level models of the actual transient fault phenomenon and latch operation to accurately propagate the fault effects to the latch outputs, after which point the zero-delay parallel fault simulator is used to speed up the simulation without any loss in accuracy. The environment is demonstrated on a set of ISCAS-89 sequential benchmark circuits.

Arc burst pattern analysis fault detection system

Abstract: A method and apparatus are provided for detecting an arcing fault on a power line carrying a load current. Parameters indicative of power flow and possible fault events on the line, such as voltage and load current, are monitored and analyzed for an arc burst pattern exhibited by arcing faults in a power system. These arcing faults are detected by identifying bursts of each half-cycle of the fundamental current. Bursts occurring at or near a voltage peak indicate arcing on that phase. Once a faulted phase line is identified, a comparison of the current and voltage reveals whether the fault is located in a downstream direction of power flow toward customers, or upstream toward a generation station. If the fault is located downstream, the line is de-energized, and if located upstream, the line may remain energized to prevent unnecessary power outages.

Typical faults of air conditioning systems and fault detection by ARX model and extended Kalman filter

Abstract: Since faulty operation of heating, ventilating, and air-conditioning (HVAC) systems is detrimental to energy conservation, and maintenance experts are no longer able to detect faults due to the sophistication of current air-handling units (AHUs), automated fault detection and diagnosis (FDD) is increasingly important In the present study, the results of a survey about typical faults that are commonly encountered in air-handling systems are summarized, and two methods of finding abrupt faults are described To investigate the development of automated fault detection schemes, two methods to detect an abrupt fault are tested, and the effectiveness of the methods is analyzed Both are based on a mathematical model of system dynamics The first one is an autoregressive exogenous (ARX) model and the second is based on an extended Kalman filter It is shown that faults that are difficult to detect by a simple limit checker method can be detected in both cases on the basis of computer simulation by HVACSIM+

System and method for locating faults in electric power cables

Abstract: There is provided a system and method for locating faults in power distribution systems with complex topology, such as multi-phase urban networks (6), utilizing reliable time-delay techniques as well as a transponder (22) at a monitoring point to sense the arrival of the transient fault pulse and for transmitting a timing pulse a known time delay after sensing the arrival of the transient fault pulse and a calibration pulse a known time delay after transmitting the timing pulse. Installed along the power distribution system at key locations are receiver stations (4, 4a, 4b) capable of sensing the arrival of the transient fault pulse, timing pulse and calibration pulse and measuring the time intervals occurring between each. The location of the fault is then determined based on these timing intervals, known time delays and the known propagation velocity of the electric power cables in the power distribution system. Fault location accuracy is further enhanced by factoring rise-time effects of the sensed pulses into the time interval measurements.

Systems and methods for determining location of a fault on an electric utility power distribution system

Abstract: A power line fault locating system employing combinations of conducted electrical transient signals recorded at specific points in the power delivery network, radiated electromagnetic signals produced by the air-gap arc preceeding the fault current or by the lightning discharge causing the fault, and knowledge of the power line path associated therewith. The arrival time of conducted transient signals produced by the fault are detected with microsecond accuracy through use of a fault recording sensor (FRS). The low level electromagnetic radiation (VHF/UHF) caused by arcing associated with power line faults is detected at at least one arc detection sensor (ADS) located at some distance from the power line. The ADS senses the time of arrival of the radiated signal associated with the fault. These two sensors for detecting the conducted and radiated signals are coupled to a central power line fault locating analyzer (PLFLA) that receives and manipulates the information using appropriate algorithms and databanks containing geographical maps of electric utility power systems, to arrive at the power line fault location. In an alternative system embodiment, multiple ADS units located about a power distribution network determine the time of arrival of arcing information which is communicated to the PLFLA to determine the power line fault location. In a related system, the precise time of occurrence of a lightning discharge associated with a lightning-caused power line fault is combined with the arrival time of conducted signals from at least one FRS and communicated to a PLFLA.

Principles of fault tolerance

Abstract: The demand for continuously available electronic systems increases every day. Transaction processing, communications systems, and critical processes all require nonstop, fault tolerant operation. Creating a fault tolerant or highly available system can be achieved by following four basic principles: redundancy, fault isolation, fault detection and annunciation, and on-line repair. This paper is a tutorial that presents those four principles after reviewing some fundamentals of reliability and availability. It concludes with an expanded discussion on implementing redundancy. Special considerations for high availability and fault tolerance in distributed power systems are highlighted.

Method and system for identification of software application faults

Abstract: A software application fault identification method and system. The method and system include software and accompanying computer hardware platforms for detecting a software application fault, determining a severity of the fault, and identifying a source of the fault. The method and system further include software and accompanying computer hardware platforms for generating an alarm message signal based upon the detected fault, the severity determined and the identified source, as well as transmitting the alarm message signal to a remote monitoring station.

System and method for managing time for vehicle fault diagnostic apparatus

Abstract: Temporal contradictions and errors between controllers are eliminated and fault diagnosis is accurately performed by correct time. The system includes a master controller (1) for transmitting a measured time as a reference time, and a plurality of controllers (11a, 11b, 11c, ..., 11n) for determining the time relating to the fault diagnosis on the basis of the received reference time when fault data of sensors, etc., are detected.

Fault observability analysis of analog circuits in frequency domain

Abstract: We study the testability of analog circuits in the frequency domain by introducing the analog fault observability concept. The proposed algorithm indicates the set of adequate test frequencies and test nodes to increase fault observability. This approach combines a structural testing methodology with functionality verification to increase the test effectiveness and consequently the design manufacturability and reliability. We analyze the case of single fault, double, and multiple faults. Concepts such as fault masking, fault dominance, fault equivalence, and non observable fault in analog circuits are defined and then used to evaluate testability. The theoretical aspect is based on the sensitivity approach.

Method and circuit for protecting power circuits against short circuit and over current faults

Abstract: A fault protection circuit for protecting IGBT's and other non-latching semiconductor devices in power circuits, for example, power converting/inverting circuits, against phase to phase, phase to earth and shoot through short circuit faults as well as against over current faults. The circuit provides local protection for devices on the high side of such power circuits, and transfers the fault to the low side where it is detected and appropriate control circuitry is activated to latch the fault, thereby avoiding the need for isolcated sensing or feedback to protect the high side devices as well as the complete power circuit.

Method and apparatus for diagnosing fault states in a computer system

Abstract: Faults in a computer system having circuits are managed by fault detectors connected to detect fault states of respective circuits. A fault manager associates the fault states with the respective circuits. The fault manager includes a system manager connected to identify which of the circuits is causing faulty operation in the computer system. The fault detectors associated with the respective circuits are configured to detect faulty operation of and to generate fault state information for the respective circuits. A central manager is connected to accumulate fault state information from the fault detectors. One of the circuits includes a bus, and the fault state includes a bus error condition. The bus is connected to multiple devices, and the fault manager identifies which of the multiple devices causes the bus error condition. One of the circuits includes multiple modules, and the fault manager identifies fault states of the multiple modules. The modules include state machines. One of the circuits includes an internal clock, and the fault state of the circuit includes the internal clock not functioning properly. One of the circuits includes a temperature sensor, and the fault state of the circuit includes a high temperature condition detected by the temperature sensor.

Neural network approach to fault detection in electric power systems

Abstract: This paper describes a fault detector that uses artificial neural networks (ANN). It represents the first step to the development of a neural distance relay for protecting transmission lines. We envisage the fault detection problem as a pattern classification process. Our suggested approach is based on the fact that when a fault occurs, a change in the system impedance takes place and, as a consequence, the current phase and amplitude change. The ANN-based fault detector is trained to detect this changes as indicators of the instant of fault inception. Results showing the performance of the fault detector are presented in the paper, indicating that it is fast, robust and accurate.

Fault behavior observation of a microprocessor system through a VHDL simulation-based fault injection experiment

Abstract: Evaluating and possibly improving the fault tolerance and error detecting mechanisms is becoming a key issue when designing safety-critical electronic systems. The proposed approach is based on simulation-based fault injection and allows the analysis of the system behavior when faults occur. The paper describes how a microprocessor board employed in an automated light-metro control system has been modeled in VHDL and a Fault Injection Environment has been set up using a commercial simulator. Preliminary results about the effectiveness of the hardware fault-detection mechanisms are also reported. Such results will address the activity of experimental evaluation in subsequent phases of the validation process.

Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits

Abstract: A new fault modelling scheme for integrated analogue CMOS circuits referred to as Local Layout Realistic Fault Mapping is introduced. It is aimed at realistic fault assumptions prior to the final layout by investigating typical "local" layout structures of analogue designs. Specific defects are assumed and their electrical failure modes are evaluated and mapped onto appropriate model faults. It is shown that some assumed hard faults at the schematic level are unrealistic and unlikely and that new types of fault constellations emerge including multiple or complex faults. Beside the different distribution of faults the overall number of faults decreases whereof additional realistic soft faults emerge. For an operational CMOS amplifier the overall number of 47 single hard faults assumed at schematic level dropped to 27 realistic and likely hard faults.

An implementation of a hybrid intelligent tool for distribution system fault diagnosis

Abstract: The common fault in distribution systems due to line outages consists of single-line-to-ground (SLG) faults, with low or high fault impedance. The presence of arcing is commonplace in high impedance SLG faults. Recently, artificial intelligence (AI) based techniques have been introduced for low/high impedance fault diagnosis in ungrounded distribution systems and high-impedance fault diagnosis in grounded distribution systems. So far no tool has been developed to identify, locate and classify faults on grounded and ungrounded systems. This paper describes an integrated package for fault diagnosis in either grounded or ungrounded distribution systems. It utilizes rule-based schemes as well as artificial neural networks (ANN) to detect, classify and locate faults. Its application on sample test data as well as field test data are reported in the paper.

Ground fault detector for line-powered telephone network

Abstract: A ground fault detection and line power supply control system protects telecommunication service personnel working on line-powered telephone circuits from ground faults, without requiring that the line power supply be disconnected or shut down prior to a technician working on the line. A ground fault loop sensing current is sourced from an auxiliary DC voltage source that is separate and distinct from the line power supply. This auxiliary DC voltage source is coupled through a ground fault current sense resistor to one side of the powered line, so that detection of a ground fault condition is not dependent upon the supply of current from the potentially hazardous line supply. If a ground fault occurs through either or both of the powered lines, the current flow through the sense resistor will exceed a prescribed threshold, and initiate operation of a switching circuit within the line-powering equipment, thereby rapidly reducing power to the telephone line until the ground fault is cleared or the loop power supply is reset.

An Evaluation of the Error Detection Mechanisms in MARS Using Software-Implemented Fault Injection

Abstract: The concept of fail-silent nodes greatly simplifies the design and safety proof of highly dependable fault-tolerant computer systems. The MAintainable Real-Time System (MARS) is a computer system where the hardware, operating system, and application level error detection mechanisms are designed to ensure the fail silence of nodes with a high probability.

Accurate fault location and protection scheme for power cable using fault generated high frequency voltage transients

Abstract: A new technique for accurate fault location and protection of distribution cable is presented in the paper. A specially designed transient capturing unit is used to extract the fault generated high frequency voltage transient signals from the distribution cable system. The travelling time of the high frequency signal is used to determine the fault position. The scheme is insensitive to fault type, fault resistance, fault inception angle and system source configuration. Studies show that the proposed technique is able to offer a very high accuracy in both fault location and fault detection.

Dynamic diagnosis of sequential circuits based on stuck-at faults

Abstract: A dynamic diagnosis scheme for synchronous sequential circuits is proposed. In contrast with schemes like fault dictionaries no prior computation and storage of fault symptoms is performed. The technique combines cause-effect and effect-cause strategies. Cause-effect analysis is performed by single stuck at fault simulation followed by a matching algorithm. Effect-cause analysis is performed by an error propagation back-trace starting from the falling outputs. The error propagation back-trace eliminates from consideration faults that could not have caused the failing symptoms. The procedure is exact for defects behaving as single stuck-at faults. Experimental results are provided for the ISCAS89 benchmark circuits.

Hierarchical fault modeling for linear analog circuits

Abstract: This paper presents a hierarchical fault modeling approach for catastrophic as well as out-of-specification (parametric) faults in analog circuits. These include both, ac and dc faults in passive as well as active components. The fault models are based on functional error characterization. Case studies based on CMOS and nMOS operational amplifiers are discussed, and a full listing of derived behavioral fault models is presented. These fault models are then mapped to the faulty behavior at the macro-circuit level. Application of these fault models in an efficient fault simulator for analog circuits is also described.

An exact non-enumerative fault simulator for path-delay faults

Abstract: The present an efficient path-delay fault (PDF) simulator that does not involve enumeration of paths. Our method calculates the exact fault coverage, and identifies all tested faults in any circuit with a large number of paths. We present a new data structure, called the Path-Status Graph (PSG), to efficiently hold the status of each PDP in the circuit, i.e., whether or not the PDF is tested. The key to this efficiency is in breaking the information into pieces and distributing it over the data structure and in retaining all or part of the reconverging fanout structure of the circuit in the PSG. Thus, an exponential number of PDFs can share the same piece of information. Using one thousand random tests, we simulated all of the approximately 10/sup 20/ PDFs in the circuit c6288 and determined that 4.4 billion faults were detected. This number is larger by over three orders of magnitude compared to what was possible with previously reported methods.

Error injection aimed at fault removal in fault tolerance mechanisms-criteria for error selection using field data on software faults

Abstract: Fault injection allows a detailed study of complex interactions between faults and fault handling mechanisms. It can be a useful complement to analytical modeling and formal verification techniques in the testing of fault tolerant systems. However, work on fault injection has not matured adequately to provide industry with cost effective alternatives for the validation of fault tolerant systems. This study analyzes 408 customer discovered faults (defects) in a release of a large operating system product. We discuss methods to select the error types for an error injection experiment in the system test environment, aimed at fault removal. Using four levels of severity and a total of 24 error types as recorded in the customer defects records, we analyze the faults in terms of fault types and system test triggers as defined in ODC. Our work shows examples of criteria that can be used to select errors for injection that use the information from the field reported defects.

Defect-oriented experiments in fault modelling and fault simulation of microsystem components

Abstract: Based on fault simulation experiments with two microsystems, a resonant silicon beam force sensor and a miniature opto-electric transformer, this paper demonstrates the necessity to consider the interrelations between nominal system models, fault models, the construction of simulation models being capable of injecting faults, and the representation of faults in a fault list of a fault simulator from the very beginning. Some suggestions will be discussed how to tackle these problems occurring in fault modelling and fault simulation of microsystems.