Showing papers on "FET amplifier published in 2002"

Vertical MOSFET SRAM cell

Abstract: A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.

Temperature sensor and method for operating a temperature sensor

Abstract: The invention relates to a temperature sensor having a first FET transistor circuit and a second FET transistor circuit and also to a method for operating a temperature sensor. Both FET transistor circuits are operated at an operating point that lies outside the temperature-independent operating point. The difference between the voltages at the first and second FET transistor circuits is evaluated as a measure of the temperature at one of the FET transistor circuits. The invention enables the temperature sensor to provide a relatively large output signal even in the case of only small changes in temperature.

Switched gain amplifier circuit

Abstract: An amplifier chain that switches between a saturated mode of operation and a linear mode of operation comprises at least two amplifier stages. A switch is associated with the first amplifier stage and dampens the gain of the amplifier chain when the switch is closed. In a first embodiment, this is done by bypassing the first amplifier stage. In second and third embodiments, this is done by providing a feedback loop to the first amplifier stage. Dynamic device scaling and changing the bias may also be used to affect the performance of the amplifier chain.

Sense amplifying circuit and method

Abstract: A sense amplifier for use in memory devices. The sense amplifier may include a pair of cross-coupled inverters, each inverter including at least two transistors. The sense amplifier may further include a first capacitor coupled to a first input/output terminal of the sense amplifier and a second capacitor coupled to a second input/output terminal thereof. A change in voltage differential appearing across the input/output terminals bootstraps the cross-coupled inverters to facilitate activation and deactivation of the transistors in the cross-coupled inverters. Consequently, response time of the sense amplifier is reduced.

System and method for rf signal amplification

Abstract: A branched power amplifier circuit includes two or more amplifier segments or branches, each with a corresponding lossy modulator. The branched power amplifier may be dynamically resized by enabling different ones of its branches to deliver peak efficiency at a number of different amplifier output power levels. Each amplifier branch operates in a saturated mode and selectively amplifies an RF input signal. The lossy modulators provide either supply voltage or supply current modulation to corresponding amplifier branches, thus imparting highly linear amplitude modulation to the overall output signal generated by branched power amplifier, despite its saturated mode operation. The branched power amplifier circuit may be configured such that particular combinations of segments have peak efficiencies matched to the needs of one or more air interface standards used in wireless mobile communication systems.

Composite amplifier structure

Abstract: A composite power amplifier structure includes a first power amplifier (PAN+1) configured as an auxiliary amplifier of a Doherty amplifier and connected to an output node and an even number of further power amplifiers configured into at least one Chireix pair (PA 1,1 + PA 1,2 ...PA N,1 + PA N,2) connected to the same output node. The Chireix pairs are driven (40) at least partially in outphasing modes and the first power amplifier is driven (40) in the same manner as the auxiliary amplifier of a Doherty amplifier.

HEMT-HBT doherty microwave amplifier

Abstract: A microwave amplifier and more particularly to a microwave amplifier configured as a Doherty amplifier. The amplifier includes a carrier amplifier, a peak amplifier, a Lange coupler at the input of the amplifiers and quarter wave amplifier at the output of the amplifiers. In order to further increase the efficiency, the Doherty amplifier is formed from HEMT/HBT technology to take advantage of the low-noise performance of HEMTs and the high-linearity of HBTs to form a relatively efficient amplifier that functions as a low-noise amplifier at low power levels and automatically switches to high-power amplification for relatively high-impact RF power levels.

Asymmetrically biased high linearity balanced amplifier

Abstract: A microwave amplifier and more particularly to a microwave amplifier configured as a Doherty amplifier. In particular, the amplifier includes a carrier amplifier, a peak amplifier a Lange coupler at the input of the amplifiers and quarter wave amplifier at the output of the amplifiers. In order to improve isolation between the amplifiers to minimize the dependence of each amplifier's inter-modulation (IM) performance on the others, matching networks are provided, coupled to the output of the amplifiers. In addition, the microwave power amplifier includes electronic tuning which allows for improved inter-modulation distortion over a wide input power dynamic range, which allows the IM performance of the microwave amplifier to be adjusted for the operating frequency of the amplifier.

Variable gain low-noise amplifier for a wireless terminal

Abstract: A variable gain, low noise amplifier is described, which is suitable as the input amplifier for a wireless terminal, or as the pre-amplifier stage of a wireless terminal transmitter. The amplifier may achieve variable gain by deploying a network of transistors in a parallel array, each independently selectable by a PMOS switch, and providing the variable resistance for the resonant circuit. Power dissipation can also be mitigated by using a network of driving transistors, each independently selectable by a PMOS switch. The resonant frequency of the amplifier may be made tunable by providing a selection of optional pull-up capacitors.

A high-power Ka-band quasi-optical amplifier array

Abstract: Results for a high-power Ka-band quasi-optical amplifier array are presented in this paper. The amplifier consists of a 45-element double-sided active array with a hard-horn feed. Excess heat is removed via a metal carrier integrated into the array with liquid cooling at the periphery. Each unit cell of the array consists of transmitting and receiving patch antennas, driver and power amplifier monolithic microwave integrated circuits on input and output layers, and a through-plate coaxial transition, which connects the input and output layers. An estimated 25 W is radiated when the amplifier is used as an antenna feed, otherwise 13 W is collected into waveguide. Experimental results and construction details are discussed.

Current probe device having an integrated amplifier

Abstract: A measurement system is provided that includes a probe device having an integrated amplifier. The integrated amplifier may be a transimpedence amplifier that amplifies input current to an output voltage.

Composite amplifier with optimized linearity and efficiency

Abstract: The invention relates to a composite amplifier (500) based on a main amplifier (510) and an auxiliary amplifier (520), and compensation for non-linear amplifier behavior by means of respective non-linear models (570, 575) of parasitics. In order to provide proper excitation of the non-linear models, a filter network (560) based on a linear model of the output network of the composite amplifier is provided. The linear filter network (560) basically determines ideal output node voltages, which are used as input to the respective non-linear models for generating appropriate compensation signals. The compensation signals are finally merged into the input signals of the respective sub-amplifiers (510, 520), thus effectively compensating for the effects of the non-linear parasitics.

System and method for closed loop VSWR correction and tuning in RF power amplifiers

Abstract: A system and method is provided to compensate an amplifier circuit for changes in a load impedance in order to maintain a substantially optimum performance for the amplifier. More specifically, if the load impedance increases, then the amplifier is reconfigured to produce an output impedance that is likewise increased. One way of reconfiguring the amplifier for a load impedance increase is to increase the supply voltage to the device. The increase in the supply voltage to the device increases the rail to rail operation of the device. This would allow more dynamic range for the system performance. Assuming the current is substantially constant, the impedance seen the output of the amplifier will increase and be multiplied up to the impedance desired by the load resulting in a more optimum power transfer. Other parameters, such as the input drive and bias voltage to the amplifier can be changed in order to improve the performance of the amplifier.

Integrated circuit low noise amplifier and applications thereof

Abstract: An integrated low noise amplifier includes an on-chip balun, a line impedance matching circuit and an on-chip differential amplifier. The on-chip balun is operably coupled to convert a single ended signal into a differential signal. The line impedance matching circuit is operably coupled to the primary of the on-chip balun to provide impedance matching for a line carrying the single ended signal. The on-chip differential amplifier is operably coupled to amplify the differential signal and is impedance matched to the secondary of the on-chip balun.

Power factor controller

Abstract: A drive with a high impedance input, low impedance output is created. When a switching or driving action requiring the sourcing and sinking of current from a common node in a wide frequency range is desired, the invention allows the creation of a simple, efficient, two switch drive system that functions across a wide range of conditions. The circuit uses a discrete N-Channel FET paired with discrete PNP transistors. A high impedance input node is formed by connecting the FET gate to the transistor base. The differential threshold voltage that exists between the FET gate and the transistor base prevents the two devices from generating conflicting currents at the output node formed by the common source emitter. The circuit further lends itself to output waveform variations as may be required for various drive strategies by manipulating the input signal processing to custom modify the resulting output voltage and current.

RF transistor amplifier linearity using suppressed third order transconductance

Abstract: The linearity of a transistor amplifier comprising a plurality of transistors operating parallel is improved by reducing the odd order transconductance derivatives of signals generated by the transistors. The transistors can be provided in groups with each group having a different bias voltage applied thereto or each group of transistors can have a different input signal applied thereto. The groups of transistors can have different physical parameters such as the width to length ratio of gates in field effect transistors and threshold voltages for the transistors.

A power amplifier module with distortion compensation

Abstract: The invention relates to a power amplifier module comprising a first amplifier (2) having a first front-end (4) and a first backend amplifier stage (5) and a second amplifier (3) having a second front-end (6) and a second backend amplifier stage (7), the first amplifier and the second amplifier being arranged in a Bridge Tied Load (BTL) configuration with feedback over the load, characterized in that the first and the second backend amplifier stages having point symmetrical transfer functions with respect to the origin, the input current i1 of the first backend amplifier stage being substantially equal to the input current i2 of the second backend amplifier stage.

Distributed amplifier having separately biased sections

Abstract: A distributed amplifier (40) comprising an input transmission line (48), an output transmission line (50) and N amplifier sections (42,44,46), and N biasing sources (82) configured to provide N independent biasing voltages for each transistor (52) of the N amplifier sections (42,44,46) for active operation as such that when a first independent biasing voltage of a first transistor is modified the first transistor is configured for a non-active operation and an output power of the distributed amplifier (40) is reduced without a substantial degradation in an efficiency of the distributed amplifier (40).

Ultrahigh-efficiency power amplifier for space radar applications

Abstract: This paper describes a broad-band switch mode power amplifier based on the indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. The amplifier combines the alternative Class-E mode of operation with a harmonic termination technique that minimizes the insertion loss of matching circuitry to obtain ultrahigh-efficiency operation at X-band. For broad-band Class-E performance, the amplifiers output network employs a transmission line topology to achieve broad-band harmonic terminations while providing the optimal fundamental impedance to shape the output current and voltage waveforms of the device for maximum efficiency performance. As a result, 65% power-added efficiency (PAE) was achieved at 10 GHz. Over the frequency band of 9-11 GHz, the power amplifier achieved 49%-65% PAE, 18-22 dBm of output power, and 8-11 dB gain at 4 V supply. The reported power amplifier achieved what is believed to be the best PAE performance at 10 GHz and the widest bandwidth for a switch-mode design at X-band.

Switchable gain amplifier

Abstract: A switchable gain amplifier for use in mobile communications devices is provided, having a first amplifier stage having a first gain, a second amplifier stage connected in parallel with the first amplifier stage. The first and second amplifier stage have different gains and a gain controller, connected to the first amplifier stage and to the second amplifier stage, enables only one of the amplifier stages at a time.

Amplifier circuits and methods

Abstract: Embodiments of the present invention provide an amplifier circuit and method that can be used to save power or reduce distortion in an electronic system, such as a wireless communication system. In one embodiment, the present invention includes an amplifier circuit comprising a transistor having a gate terminal, drain terminal, body terminal, and a load. An input signal has different signal envelopes during different time periods. A control signal coupled to the body terminal is used to change the voltage on the body terminal when the input receives different envelopes. Accordingly, the amplifier can be biased to use less power when lower envelopes are being received. Electronic systems, such as wireless communication systems, can realize advantageous performance enhancements by utilizing the amplifier and other techniques employed by embodiments of the present invention.

Systems and methods for on-chip impedance termination

Abstract: Techniques for on-chip impedance termination are provided that substantially reduce the number of external resistors that are need to provide impedance termination at a plurality of pairs of differential input/output (I/O) pins. On-chip impedance termination circuits of the present invention may include an amplifier, a feedback loop, and an impedance termination circuit. A reference voltage is provided to a first input terminal of the amplifier. A feedback loop is coupled between an output terminal of the amplifier and a second input terminal of the amplifier. The amplifier drives its output voltage so that the voltage at the second input terminal matches the voltage at the first input terminal. The output voltage of the amplifier determines the resistance of the impedance termination circuit. The impedance termination circuit is coupled between differential I/O pins.

Improved design technique of a microwave class-E power amplifier with finite switching-on resistance

Abstract: The class-E amplifier is a highly efficient amplifier for microwave power applications. Due to the complexity involved, previous analytical efforts assumed either zero switch resistance and/or infinite drain (collector) inductance, which resulted in less than optimum designs. In this paper, we take the effect of both the finite switching-on resistance and finite drain inductance into account, and present an improved and optimized design technique. A 1.9 GHz CMOS class-E power amplifier, which can deliver 0.25 W of output power, was analyzed as an example of this new design technique. Excellent agreement between the theoretical analysis and simulation results is reported, pointing the way towards the optimized design of the class-E stage for microwave applications.

A low power fully integrated bandpass operational amplifier for biomedical neural recording applications

Abstract: This paper presents a low power fully integrated bandpass amplifier for a variety of biomedical neural recording applications. A standard two-stage CMOS amplifier in a closed-loop resistive feedback configuration provides stable AC gain of 39.5 dB at 1 kHz. A PMOS input transistor, biased near the sub-threshold region acting as a high value resistor in the range of hundreds of mega ohms, is utilized to clamp the large and random DC open circuit potential that normally exists at the electrode-electrolyte interface. The 3 dB bandwidth of the amplifier is measured to be 26 Hz - 6.5 kHz and the tolerable DC input range is measured to be at least 1 V. The amplifier measures 0.107 mm/sup 2/ in die area and dissipates 133 /spl mu/W from a 3 V power supply. It is fabricated in MOSIS AMI 1.5 /spl mu/m double poly double metal n-well CMOS process. Bench tests show complete functionality of the amplifier in both light and dark conditions and for a wide range of recording electrode capacitance.

High-performance low-power current sense amplifier using a cross-coupled current-mirror configuration

Abstract: A high-performance current sense amplifier employing a cross-coupled current-mirror configuration is presented. The circuit is designed for low-voltage low-power SRAM applications. Its sensing speed is independent of the bit-line capacitances and is only slightly sensitive to the data-line capacitances. Simulation results have shown that the new sense amplifier gives performance leverage over the conventional sense amplifier circuits in terms of speed and power.

Voltage-controlled oscillator with an automatic amplitude control circuit

Abstract: A VCO having an automatic amplitude control circuit In the form of a sensing amplifier provided in the feedback loop to sense the oscillator amplitude and draw current away only when the positive peak voltage Is above a certain value. In general, any amplifier may be used in the feedback loop that outputs current proportional to a peak positive input (in a non-linear and asymmetric fashion with respect to the changing voltage). In one example, the amplifier in the feedback loop comprises first and second transistors that are set nominally in cut off and behave as class C amplifiers. The advantage of this amplifier transistor configuration is that the amplifier they form has a low load on the LC tank circuit and a high input impedance.

Two-electrode biopotential amplifier with current-driven inputs

Abstract: A circuit was developed for a differential two-electrode biopotential amplifier. Current sources at the amplifier inputs were controlled by the common-mode voltage. This principle is well known in telephony for interfacing the telephone line with analogue-type phones. A low impedance of about 1 kΩ was obtained between each input and the common point of the circuit. The differential input impedance of 60 MΩ was obtained with the use of precision resistors. Considerable reduction in the common-mode voltages of more than 200 times resulted. The circuit can be useful for biosignal acquisition from subjects in areas of very high electromagnetic fields, where high common-mode voltages could saturate the input amplifier stages.

High-frequency power amplifying apparatus

Abstract: A high-frequency power amplifying apparatus includes a plurality of series-connected amplifiers, a power controller for selectively supplying an output terminal with an output from a desired one amplifier in accordance with a demanded output power and for causing one or more amplifiers downstream of the desired one amplifier to be in a cutoff state, and an output delay line connected between the output terminal and the final-stage amplifier and having a line length thereof providing the final-stage amplifier with a high impedance as viewed from the output terminal when the final-stage amplifier is in a cutoff state.

A fully integrated broad-band amplifier MMIC employing a novel chip-size package

Abstract: In this work, we used a novel RF chip-size package (CSP) to develop a broad-band amplifier monolithic microwave integrated circuit (MMIC), including all the matching and biasing components, for Ku- and K-band applications. By utilizing an anisotropic conductive film for the RF-CSP, the fabrication process for the packaged amplifier MMIC could be simplified and made cost effective. STO (SrTiO/sub 3/) capacitors were employed to integrate the dc biasing components on the MMIC. A novel pre-matching technique was used for the gate input and drain output of the FETs to achieve a broad-band design for the amplifier MMIC without any loss of gain. To improve the circuit stability of the amplifier MMIC in the out-of-band, a parallel RC circuit was employed at the input of the amplifier MMIC. The packaged amplifier MMIC exhibited good RF performance and stability over a wide frequency range. This work is the first report of a fully integrated CSP amplifier MMIC successfully operating in the Ku-/K-band.

A high-performance cryogenic amplifier based on a radio-frequency single electron transistor

Abstract: We demonstrate a high-performance cryogenic amplifier based on a radio-frequency single-electron- transistor (rf-SET). The high charge sensitivity and large bandwidth of the rf-SET, along with low power dissipation, low capacitance and on-chip integrability, make it a good candidate for a general-purpose cryogenic amplifier for high impedance sources. We measure a large-gate rf-SET with an open-loop voltage noise of 30 nV/(Hz), among the lowest reported voltage noise figures for a SET. Using a closed-loop transimpedance configuration, the amplifier shows almost 2 orders of magnitude increase in dynamic range, a 3 dB bandwidth of 30 kHz, and a transimpedance gain of 50 V/μA for a cryogenic 1 MΩ load resistor. The performance of this amplifier is already sufficient for use as an integrated readout with some types of high-performance cryogenic detectors for astrophysics.