Showing papers on "Gate oxide published in 1983"

Method of making low resistance polysilicon gate transistors and low resistance interconnections therefor via gas deposited in-situ doped amorphous layer and heat-treatment

Abstract: In the disclosed method, a transistor is fabricated by depositing an unpatterned layer of silicon on an insulating layer over a surface of a semiconductor substrate, with the silicon layer being deposited in an amorphous state to improve its uniformity in thickness and smoothness. Subsequently, while the silicon layer is still in the amorphous state, it is patterned by removing selected portions to form a gate. This patterning in the amorphous state improves the gates edge definition. Thereafter, the patterned amorphous silicon layer is heated to change it to polycrystalline silicon, thereby increasing its stability and conductivity.

Effects of hot-carrier trapping in n- and p-channel MOSFET's

Abstract: Detailed measurements of hot-carrier gate current and its trapping effects were studied on both n- and p-channel MOSFET's down to submicrometer channel lengths. Comparison of the measurements for these two types of devices is made. No hot-hole gate current or hot-hole trapping was detected in p-channel MOSFET's. A hot-electron gate current is present not only in n-channel MOSFET's, but also in p-channel MOSFET's where the current is increased by hot-electron trapping. By trapping hot electrons uniformly over the channel in n-MOSFET's, it was shown that hot-electron trapping produces only negative oxide charge without generating interface traps.

Manufacture of thin film semiconductor device

Abstract: PURPOSE: To turn a gate electrode into salicide, and reduce gate line resistance, by forming a high melting point metal film on a polycrystalline silicon gate electrode, and annealing the film. CONSTITUTION: After a gate oxide film is formed on a solid-phase epitaxy silicon thin film formed on a quartz substrate, a polycrystalline silicon film is deposited, and a polycrystalline silicon gate electrode 2-5 is formed by patterning. Impurities are ion-implanted, and a source region 3-6 and a drain region 3-7 are formed in a self-alignment manner. A high melting point metal film 3-9 is formed. The polycrystalline silicon gate electrode 2-5 is turned into salicide by annealing, and a salicide layer 3-10 is formed. By selectively eliminating the high melting point metal, a salicide gate electrode 3-12 is formed. After a contact hole is formed in an interlayer insulating film 3-13, a source electrode and a drain electrode are formed, and a thin film transistor whose gate line resistance is small is formed. COPYRIGHT: (C)1995,JPO

Nonvolatile MNOS memory

Abstract: A nonvolatile memory which has both the merits of a floating gate type EEPROM and an MNOS type EEPROM and which can be written into and erased with low voltages is disclosed. Each memory element in the nonvolatile memory has a floating gate, a control gate, a gate insulator film between a semiconductor body and the floating gate, and an inter-layer insulator film between the control gate and the floating gate. The gate insulator film is made up of a very thin SiO2 film and a thin Si3 N4 film formed thereon. The charge centroid of charges injected for storing data lies within the floating gate, not within the Si3 N4 film.

Floating gate memory device with facing asperities on floating and control gates

Abstract: A floating gate memory device includes a substrate of semiconductor material having on a surface thereof a layer of insulating material. On the insulating layer is a floating gate of conductive polycrystalline silicon with the floating gate having a textured outer surface and relatively smoother sidewalls. A second layer of insulating material extends over the outer surface and sidewalls of the floating gate. The portion of the second insulating material over the outer surface of the floating gate has a textured surface and is thinner than the portions of the second insulating layer over the sidewalls of the floating gate. A control gate is over the second insulating layer and extends over the outer surface and sidewalls of the floating gate. The control gate is of conductive polycrystalline silicon and has an inner surface portion over the textured outer surface of the control gate which is textured and has undulations which substantially follow the undulations of the textured surface of the floating gate.

Method of making high density VMOS electrically-programmable ROM

Abstract: A method of making an electrically-programmable memory array in which the memory elements are capacitor devices formed in anisotropically etched V-grooves, providing enhanced dielectric breakdown at the apex of the groove. After breakdown, a memory element exhibits a low resistance to a grounded substrate. The method includes forming access transistors in series with the memory elements, and polycrystalline silicon, deposited to form control gates of the access transistors, also forms address lines. Oxide is formed in the V-groove thinner than the gate oxide thickness formed for the access transistor, providing a lower programming voltage. These factors provide a very small, high speed device.

Improving the reverse recovery of power mosfet integral diodes by electron irradiation

Abstract: This paper demonstrates that controlled electron irradiation of silicon power MOSFET devices can be used significantly improve the reverse recovery characteristics of their integral reverse conducting diodes without adversely affecting the MOSFET characteristics. By using 3 MeV electron irradiation at room temperature it was found that the reverse recovery charge in the integral diode could be continuously reduced in a well controlled manner from over 500 nC to less than 100 nC without any significant increase in the forward voltage drop of the integral diode under typical operating peak currents. The reverse recovery time was also observed to decrease from 3 microseconds to less than 200 nsec when the radiation dose was increased from 0 to 16 Megarads. The damage produced in gate oxide of the MOSFET due to the electron radiation damage was found to cause an undersirable decrease in the gate threshold voltage. This resulted in excessive channel leakage current flow in the MOSFET at zero gate bias. It was found that this channel leakage current was substantially reduced by annealling the devices at 140°C without influencing the integral diode reverse recovery speed. Thus, the electron irradiation technique was found to be effective in controlling the integral diode reverse recovery characteristics without any degradation of the power MOSFET characteristics.

Self-aligned metal process for field effect transistor integrated circuits using polycrystalline silicon gate electrodes

Abstract: A process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits The method for forming integrated circuits with this structure includes forming openings in a first polycrystalline silicon layer overlying an insulator by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces The openings are in those areas designated to be the gate regions of the field effect transistors A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body The gate dielectric is formed hereat A second polycrystalline silicon gate electrode is formed over the gate dielectric and between certain of said narrow dimensioned regions The remaining first polycrystalline silicon layer is then removed by etching to leave the narrow dimensioned regions on the major surface of the silicon body A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source/drain PN regions A blanket layer of a plastic material is used to planarize the surface by reactive ion etching the plastic material and the conductive layer until the tops of the narrow dimensioned regions are reached The plastic material is then removed leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having a thickness dimension in the order of a micron or less The source and drain electrodes are thusly formed

Radiation-Induced Interface States of Poly-Si Gate MOS Capacitors Using Low Temperature Gate Oxidation

Abstract: The effect of gate oxidation temperature on radiation-induced flatband and threshold voltage shifts and interface state buildup for steady-state Co60 irradiation have been studied for poly-Si gate MOS capacitors with pyrogenic and dry gate oxides. The smallest radiation-induced flatband and threshold voltage shifts can be achieved with a pyrogenic oxide grown at 850°C. Total dose effects, applied gate bias during the irradiation and oxide thickness dependence were also evaluated for low temperature pyrogenic oxide MOS capacitors. We obtained a 2/3 power law dependence of radiation-induced interface states on the total dose and the oxide thickness.

Method for manufacturing semiconductor Bi-CMOS device

Abstract: A method for forming a Bi-CMOS structure, wherein a vertical npn transistor and CMOS transistors are formed on a single semiconductor substrate, is disclosed. After forming a p-type epitaxial silicon layer on a p-type silicon substrate with a plurality of n+ -type buried layers therein, n-type wells are formed to extend to the n+ -type buried layers. Selective oxidation is performed to form field oxide films so as to define an n-type element region for the npn transistor, an n-type element region for the p-channel MOS transistor, and a p-type element region for the n-channel MOS transistor. An oxide film as a gate oxide film for the CMOS is formed on the surfaces of all the element regions. After forming a p-type active base region of the npn transistor by ion-implantation of boron, an emitter electrode comprising an arsenic-doped polysilicon layer is formed in contact with the p-type active base region. Gate electrodes of the CMOS are formed and have a low resistance due to doping with phosphorus and/or arsenic. Using the emitter electrode as a diffusion source, an n-type emitter region is formed. Boron is then ion-implanted to simultaneously form a p+ -type external base region and p+ -type source and drain regions of the p-channel MOS transistor. Phosphorus is ion-implanted to form an n+ -type collector contact region and n+ -type source and drain regions of the n-channel MOS transistor.

Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas

Abstract: A CMOS integrated circuit made up of complementary insulated gate field effect transistors incorporates isolation trenches formed by a combination of thermal growth of silicon dioxide and chemical vapor deposition of polycrystalline silicon to prevent air gaps. Matching of the thermal coefficient of expansion of the trench with that of the substrate minimizes pn junction leakage currents as well as positive feedback latch-up operation. To reduce the ohmic contact resistance and interconnect resistance of the transistor elements, refractory metal silicide areas of low sheet resistance are contacted with the source, drain and gate elements. The process of manufacture also employs vertical walls of silicon nitride to prevent the formation of "birds' beak" portions of increased thickness in the silicon dioxide layer of each transistor, which could degrade the high frequency performance of the device.

Floating gate memory with improved dielectric

Abstract: The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.

Semiconductor device and process for manufacturing the same

Abstract: A multilayer structure comprising a Si layer/ a refractory metal oxide layer/ a refractory metal layer/ is subjected to annealing in an atmosphere of hydrogen or an inert gas mixed with hydrogen, thereby converting the multilayer structure into a multilayer structure comprising a Si layer/an inner SiO 2 layer formed by internal oxidation of Si/a refractory metal layer. The inner SiO 2 layer is selectively formed only on the surface of the refractory metal layer, since Si is internally oxidized from the side of the refractory metal layer. In case of gate electrode of a MISFET, the gate electrode and a contact hole for source or drain electrode are positioned in self-alignment with each other via the inner SiO 2 layer. The distance between the gate electrode and the source or drain electrode is determined by the thickness of the inner SiO 2 layer. A semiconductor device with a high density and a high speed is realized.

Oxide trench structure for polysilicon gates and interconnects

Abstract: Disclosed is a manufacturing method of forming silicon gate, self-aligned MOS-type devices having submicron dimensions. After forming the gate from a highly doped polysilicon layer using a mask, the structure is subjected to a low temperature (700-750 degrees C.) thermal oxidation. Due to enhanced oxidation rate of doped silicon surfaces, a very thick oxide layer over the polysilicon gate sidewalls and a relatively thin oxide layer over the source-drain regions of the substrate are formed. The mask over the polysilicon and the oxide layer over the source-drain regions is removed and source-drain implantation is accomplished followed by selective deposition of metal (e.g. tungsten) over the source-drain regions and the polysilicon gate. In an alternative embodiment of this process, after forming the highly doped polysilicon gate using a mask, lightly doped source-drain regions which are self-aligned and in registry with the gate are formed by ion implantation. Then, low temperature thermal oxidation is accomplished growing a thick oxide over the polysilicon gate sidewalls and a thin oxide over the source-drain regions. The mask over the gate and the thin oxide over the source-drain regions is removed and by ion implantation heavily doped source-drain regions are formed in the previously formed lightly doped source-drain regions not masked by the polysilicon sidewall oxide. Selective deposition of a metal is then accomplished over the source-drain regions of the silicon substrate and the polysilicon gate.

Fabrication of metal lines for semiconductor devices

Abstract: A method of fabricating MESFET devices having a submicron line gate electrode is disclosed. The method includes the formation of a single layer of resist material on a semiconductor surface; formation of a resist cavity through optical lithography, the cavity exposing a selected portion of the semiconductor surface; depositing by way of angled evaporation at least one gate wall within said resist cavity, the gate wall defining a shaped gate cavity; depositing gate electrode material within the gate cavity, and removing the resist material. In one embodiment of the invention the gate wall is removed from the gate electrode material, leaving a free-standing electrode. In another embodiment, the gate wall is a permanent part of the electrode structure.

High power MOSFET with direct connection from connection pads to underlying silicon

Abstract: The gate electrode pad and the source electrode pad of a high power MOSFET are supported atop an oxide layer. The peripheral regions of the source electrode which surround the areas of the gate and source pads are connected at a plurality of points around their peripheries through the oxide layer to the underlying silicon. This enables rapid collection of minority carriers which were weakly injected into the region surrounding the pads when a junction beneath the pads is forward-biased.

Fast-switching insulated gate transistors

Abstract: Insulated gate transistors (IGT's) with high-speed gate turn-off capability have been developed by using electron irradiation to reduce the minority-carrier lifetime in the drift region. Gate turnoff times as low as 200 ns have been achieved. These devices have been found to offer a unique advantage in the ability to tradeoff conduction and switching losses which allows optimization of device characteristics for each application.

CMOS on buried nitride—A VLSI SOI technology

Abstract: A CMOS technology in silicon on insulator (SOI) for VLSI applications is presented. The insulator is a buried silicon nitride formed by nitrogen implantation and annealing. The CMOS devices are fabricated in the superficial monocrystalline silicon layer without an epitaxial process, 1-µm PMOS and 2-µm NMOS transistors have been realized, which have been used to built inverters, ring Oscillators, and other circuits. With 40-nm gate oxide the transistors withstand gate and drain voltages of 10 V. Mobilities, subthreshold behavior, and leakage currents are nearly the same as in bulk-CMOS devices. Ring-oscillator measurements yield inverter delay times of 230 ps and power delay products of 14 fJ.

Dynamic RAM with non-volatile back-up storage and method of operation thereof

Abstract: A dynamic random access memory having a non-volatile back-up storage capability including a latent image capability, and method of operating the memory. Each memory cell is composed of a dynamic portion and a non-volatile portion connected to the dynamic portion. The non-volatile portion is formed of a dual gate FET, one gate of which is a floating gate. A segment of DEIS (Dual Electron Injection Structure) material is provided to control the charge of the floating gate. A capacitor couples the floating gate to the source of the dual gate FET and to the data node of the cell. The second gate of the dual gate FET can be grounded to turn off the channel of the dual gate FET independent of the charge on the floating gate during normal dynamic memory operations. To perform a non-volatile storing operation, the voltage applied to the DEIS material opposite the floating gate is taken first positive and then negative. During the positive portion of the cycle, if the data at the data node is a data 0, a positive charge is stored on the floating gate, while if the data at the data node is a data 0, a positive charge is stored on the floating gate during the negative portion of the cycle. To restore the data, a data 1 is written at the data node and the second gate of the dual gate FET transistor is pulsed to thereby allow the charge stored on the floating gate to control the conductivity of the channel of the dual gate FET. If a positive charge is stored on the floating gate, the channel conducts and discharges the data node, while if a negative charge is stored on the floating gate, the channel remains non-conductive and the charge at the data node is retained.

Method for the manufacture of integrated MOS-field effect transistor circuits silicon gate technology having diffusion zones coated with silicide as low-impedance printed conductors

Abstract: A method for the manufacture of integrated MOS-field effect transistor circuits in silicon gate technology and wherein diffusion source and drain zones are coated with a high melting point silicide as low-impedance printed conductors. The diffusion zones and polysilicon gates are made low-impedance through selective deposition of the metal silicide onto surfaces thereof. The selective deposition, which proceeds by use of a reaction gas eliminating hydrogen halide, simplifies the process sequence and is fully compatible with conventional silicon gate processes. Because of the high temperature stability, preferably tantalum silicide is employed. The invention is useful in the manufacture of MOS-circuits in VLSI-technology.

Dynamic behavior of the buildup of fixed charge and interface states during hot-carrier injection in encapsulated MOSFET's

Abstract: The aging behavior of MOSFET's encapsulated with various types of capping layers was studied. Aging consisted of room-temperature pulsed gate bias operation with a drain-to-source voltage sufficient to cause avalanche multiplication in the channel. It was verified by secondary ion mass spectroscopy (SIMS) profiling that plasma silicon nitride capping layers introduce 2-4 times more hydrogen at the Si-gate oxide interface than exists in uncapped devices. Capping materials that serve as hydrogen barriers contribute to device aging by trapping hydrogen that is liberated during hot-carrier emission into the gate oxide. The aging dynamics begin with buildup of negative fixed charge in the gate oxide near the drain, followed by the buildup of positive fixed charge and interface states. The generation of these interface states and the negative fixed charge was found to have a spatial and time dependence. Long anneals at temperatures above 350°C delay the onset of the aging process. A model that accounts for these observations is proposed.

Fabrication of FETs

Abstract: A method of fabricating field effect transistors which includes control of threshold potential by an ion implantation limited to the active channel area. The active channel area is defined by a photoresist pattern. Ions are implanted into the exposed area in a concentration to achieve a desired threshold. Appropriate metals are deposited over the channel area to form a gate electrode. The photoresist is lifted off leaving the gate electrode in position over the channel area. If desired, a layer of polysilicon can be included prior to resist formation and later removed by an etchant which does not attack the gate electrode.

Method of integrating MOS devices of double and single gate structure

Abstract: A nonvolatile semiconductor memory device is provided having a MOS transistor and a floating gate type MOS transistor. The length of an overlap between a floating gate and a drain region of the floating gate type MOS transistor is made smaller than that of an overlap between the gate and the drain region of the MOS transistor.

Method of manufacturing thin film transistors and transistors made thereby

Abstract: An improved method of manufacturing thin film transistors A gate metal is patterned to form a gate electrode and a drain, gate and source contact pad for the transistor To reduce shorts and capacitance between the gate and the source or the drain, an intermetal dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges

Fabrication of polysilicon to polysilicon capacitors with a composite dielectric layer

Abstract: The present invention teaches a new method for formation of thin dielectrics over polysilicon. This technique permits the fabrication of polysilicon to polysilicon capacitors with high specific capacitance (per unit area). This technique is completely compatible with standard MOS dual polysilicon regrown gate oxide processes. The high value of specific capacitance is achieved by using a composite dielectric which has high dielectric integrity and whose thickness is completely independent of the formation of the regular gate oxide under the second polysilicon layer. No extra mask steps are required. The composite dielectric is formed as a grown or deposited oxide followed by deposited nitride which is then reoxidized. Optionally, a second oxide is deposited before reoxidation forms.

Thin film transistor having an annealed gate oxide and method of making same

Abstract: A new and improved thin film field effect transistor and method provides such a transistor having increased operating frequencies and higher output currents. The transistor includes a gate electrode having a non-coplanar surface with respect to the substrate and a deposited semiconductor material overlying the gate electrode to form a current conductor channel between a source and drain. The length of the current conduction channel is determined by the thickness of the gate electrode which can be accurately controlled. As a result, short channel lengths are possible without high precision photolithography for high output currents and fast operating speeds. Further, a gate insulator is disposed between the gate and the deposited semiconductor. The gate insulator, which can be a gate oxide, can be annealed prior to the deposition of the deposited semiconductor to provide enhanced field effect mobilities. This further increases the transistor output currents and operating speeds.

Integrated power switching semiconductor devices including igt and mosfet structures

Abstract: Hybrid power switching semiconductor devices advantageously integrate IGT and MOSFET structures. The IGT and MOSFET portions of the overall device include respective gate structures each having an associated gate electrode capacitance, and the hybrid device includes a resistance element connecting the IGT and MOSFET gates. The gate structures preferably comprise polysilicon electrodes, and the resistance element comprises a polysilicon bridge formed at the same time during device fabrication. The overall device has only a single gate terminal, which is connected relatively directly to one of the IGT and MOSFET gates, and indirectly through the resistance element to the other of the IGT and MOSFET gates such that an RC time delay network is defined. Two different types of power switching functions are achieved depending upon whether the overall device gate terminal is connected nearer the IGT gate or the MOSFET gate.

Crystallized silicon-on-insulator nonvolatile memory device

Abstract: Disclosed is a nonvolatile memory device which utilizes a laser beam recrystallized silicon layer having source-channel-drain regions. Underlying the recrystallized layer and separated therefrom by a memory dielectric is a gate in alignment with the source and drain. The gate is formed directly on a substrate of an insulative material (e.g. non-silicon material). The process of forming the above device comprises forming a conductive polysilicon gate on a substrate followed by a memory nitride layer deposition thereon. A thick oxide layer is formed over the nitride followed by removal of the thick oxide corresponding to a central portion of the gate thereby exposing the nitride therebeneath. The exposed nitride surface is thermally converted into a thin, stoichiometric memory SiO2. A doped polysilicon layer is then formed on the structure and thereafter converted to recrystallized silicon by subjecting it to laser radiation. The recrystallized silicon is patterned into the device active area and a source and drain in alignment with the underlying gate are implanted therein.

Integrated circuit employing insulated gate electrostatic induction transistor

Abstract: An insulated gate electrostatic induction transistor and an integrated circuit employing such an insulating gate electrostatic induction transistor as a drive transistor. A highly resistive channel region is provided on a semiconductor substrate of higher conductivity. A highly doped source region is formed adjacent the channel region, and a gate electrode, separated from the channel region by a thin insulating layer, is formed above the channel region. The gate electrode has a high diffusion potential with respect to the source region. The depth of the highly doped source region is less than that of a distribution of carriers in an inversion layer formed under the gate electrode.

Characteristics of TiN gate metal‐oxide‐semiconductor field effect transistors

Abstract: We have investigated the compatibility of TiN gate electrodes with standard metal‐oxide‐semiconductor (MOS) processing. Measurements were performed on MOS capacitors to determine the metal work function, flat‐band voltage, total interface charge density, mobile oxide charge density, oxide leakage current, and breakdown field. The measurement of the threshold voltage as a function of back bias on TiN gate MOS field effect transistors has revealed device characteristics which compare well with those of standard polysilicon gate devices.