Showing papers on "MOSFET published in 1993"

Comparison of 6H-SiC, 3C-SiC, and Si for power devices

Abstract: The drift region properties of 6H- and 3C-SiC-based Schottky rectifiers and power MOSFETs that result in breakdown voltages from 50 to 5000 V are defined. Using these values, the output characteristics of the devices are calculated and compared with those of Si devices. It is found that due to very low drift region resistance, 5000-V SiC Schottky rectifiers and power MOSFETs can deliver on-state current density of 100 A/cm/sup 2/ at room temperature with a forward drop of only 3.85 and 2.95 V, respectively. Both devices are expected to have excellent switching characteristics and ruggedness due to the absence of minority-carrier injection. A thermal analysis shows that 5000-V, 6H-, and 3C-SiC MOSFETs and Schottky rectifiers would be approximately 20 and 18 times smaller than corresponding Si devices, and that operation at higher temperatures and at higher breakdown voltages than conventional Si devices is possible. Also, a significant reduction in the die size is expected. >

Scaling theory for double-gate SOI MOSFET's

Abstract: A scaling theory for double-gate SOI MOSFETs, which gives guidance for device design (silicon thickness t/sub si/; gate oxide thickness t/sub ox/) that maintains a subthreshold factor for a given gate length is discussed. According to the theory, a device can be designed with a gate length of less than 0.1 mu m while maintaining the ideal subthreshold factor. This is verified numerically with a two-dimensional device simulator. >

Lateral profiling of oxide charge and interface traps near MOSFET junctions

Abstract: A technique for measuring the lateral distributions of both interface traps and trapped oxide charge near the source/drain junctions in MOSFETs is presented in detail. This technique derives from the charge pumping method, is easy to implement, and allows ready separation of the interface-trap and oxide charge components. Some illustrative results are given. The various issues involved in its implementation and its practical limitations are discussed. >

Silicon carbide switching device with rectifying-gate

Abstract: A silicon carbide switching device includes a three-terminal interconnected silicon MOSFET and silicon carbide MESFET (or JFET) in a composite substrate of silicon and silicon carbide. For three terminal operation, the gate electrode of the silicon carbide MESFET is electrically shorted to the source region of the silicon MOSFET, and the source region of the silicon carbide MESFET is electrically connected to the drain of the silicon MOSFET in the composite substrate. Accordingly, three-terminal control is provided by the source and gate electrode of the silicon MOSFET and the drain of the silicon carbide MESFET (or JFET). The switching device is designed to be normally-off and therefore blocks positive drain biases when the MOSFET gate electrode is shorted to the source electrode. At low drain biases, blocking is provided by the MOSFET, which has a nonconductive silicon active region. Higher drain biases are supported by the formation of a depletion region in the silicon carbide MESFET (or JFET). To turn-on the device, the gate electrode is biased positive and an inversion layer channel of relatively low resistance is formed in the silicon active region. The channel electrically connects the source of the silicon carbide MESFET (or JFET) with the source of the silicon MOSFET to thereby turn-on the device when a positive drain bias is applied.

Hardness-assurance and testing issues for bipolar/BiCMOS devices

Abstract: The dose-rate dependence of bipolar current-gain degradation is mapped over a wide range of dose rates. This dependence is very different from analogous MOSFET curves. Annealing experiments following irradiation show negligible change in base current at room temperature, but significant recovery at temperatures of 100 degrees C and above. In contrast to what is observed in MOSFETs, irradiation and annealing tests cannot be used to predict the low-dose-rate response of bipolar devices. A comparison of X-ray-induced and /sup 60/Co gamma-ray-induced gain degradation for bipolar transistors is reported. The role of the emitter bias during irradiation is also examined. Preliminary field-oxide capacitor studies suggest that the mechanism for the dose-rate effect may be related to charge yield in the basic surface oxides. Recommendations for hardness-assurance testing of bipolar devices include testing at dose rates below 10 rad(SiO/sub 2/)/s and applying safety factors to estimate the space-environment response. >

Bipolar-FET hybrid-mode operation of quarter-micrometer SOI MOSFETs (MESFETs read MOSFETs)

Abstract: A hybrid mode of device operation, in which both bipolar and MOSFET currents flow simultaneously, has been experimentally investigated using quarter-micrometer-channel-length MOSFET's which were fabricated on SIMOX silicon-on-insulator substrates. This mode of device operation is achieved by connecting the gate of a non-fully-depleted SOI MOSFET to the edges of its floating body. Both the maximum G/sub m/ and current drive at 1.5* higher than the MOSFET's normal mode. Bipolar-junction-transistor (BJT)-like 60-mV/decade turn-off behavior is also achieved. This mode of operation is very promising for low-voltage, low-power, very-high-speed logic as well as for on-chip analog functions. >

Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs

Abstract: MOSFETs subjected to large-signal gate-source voltage pulses on microsecond to millisecond time scales exhibit transient threshold voltage shifts which relax over considerably longer periods of time. This problem is important in high-accuracy analog circuits where it can cause errors at the 12 b level and above. In this paper, transient threshold voltage shifts are characterized with respect to their dependence on stress amplitude and duration, relaxation time, gate bias, substrate bias, drain voltage, temperature, and channel width and length. In contrast to previous studies, threshold voltage shifts are measured at time and voltage scales relevant to analog circuits, and are shown to occur even when the effects of Fowler-Nordheim tunneling, avalanche injection, hot carriers, trap generation, self-heating, mobile ions, and dipolar polarizations are absent. A new model is proposed in which channel charge carriers tunnel to and from near-interface oxide traps by one of three parallel pathways. Transitions may occur elastically, by direct tunneling between the silicon band edges and an oxide trap, or inelastically, by tunneling in conjunction with a thermal transition in the insulator or at the Si-SiO/sub 2/ interface. Simulations based on this model show excellent agreement with experimental results. The threshold voltage shifts are also shown to be correlated with 1/f noise, in corroboration of the tunneling model. Techniques for the minimization and modeling of errors in circuits are presented. >

Voltage-driven type semiconductor device

Abstract: According to the present invention, a MOSFET is formed of an n source, a p well, an n drain and a MOS gate electrode, a bipolar transistor is formed of an n emitter, a p base and an n collector formed in sequential order adjacent to the n drain. These transistors are formed by being merged with each other by the contact of n drain and the n emitter of the same conductivity type. Holes are injected into the drain of a voltage-driven type transistor comprised of the MOSFET from the bipolar transistor having a very small collector saturation resistance. With this, it is possible to give rise to conductivity modulation in the drain of the MOSFET, while the power dissipation of the voltage-driven type semiconductor device becomes very small.

Experimental Study Of Threshold Voltage Fluctuations Using An 8k MOSFET's Array

Abstract: Increasing the number of transistors and scaling down the dimensions of the transistors in ULSIs are considered to enhance the fluctuations of the transistor characteristics, from the viewpoint of the channel doping fluctuations [l], 121. However, the statistical study of the transistor fluctuations has not been experimentally performed. In this paper, we have focussed on the threshold voltage V,, fluctuatioris of 8k NMOSFET’s in a less than 0.8mm2 area, using a newly developed 256x32 transistor array with a 8bit binary counter. It is experimentally shown for the first time that the V,, fluctuatioris depend on the channel length and the gate oxide thiclmess. Furthermore, it is directly demonstrated that the V,, fluctuations correlate with the dopant number fluctuations of the channel region.

A simple and efficient synchronous rectifier for forward DC-DC converters

Abstract: A simple and efficient MOSFET synchronous rectification circuit suitable for forward DC-DC power converters is proposed. The main feature of this circuit is the addition of a capacitor in parallel with the drain source of the MOSFET used as a rectifying device. This capacitor extends the conduction period of the MOSFET used as a freewheeling device. As a result, a 92% efficiency at 5 V for 10 A output is achieved. >

Silicon MOSFETs, the microwave device technology for the 1990s

Abstract: Silicon MOSFET technology using 1.5- mu m gate lengths has demonstrated excellent performance for 900-MHz applications. Circuit results for low-noise amplifiers, power amplifiers, mixers, and oscillators using this technology are discussed in comparison to other device technologies. Device results for 0.6- mu m-gate-length devices showing the microwave performance of silicon MOS transistors are discussed. These results, together with scaling predictions, indicate that microwave silicon MOSFETs will play a major role in the 1990s. The performance of devices with 0.6- mu m gate lengths indicates that silicon MOS will be the FET technology of choice for applications below 3 GHz. Advantages such as high voltage characteristics, low thermal conductivity of silicon, and the high operating junction temperature make silicon MOS a technology with immense potential for high-voltage X-band power applications. >

On-chip p-MOSFET dosimetry (CMOS ICs)

Abstract: On-chip p-FETs were developed to monitor the radiation dose of n-well CMOS ICs by monitoring threshold voltage shifts due to radiation-induced oxide and interface charge. The design employs closed-geometry FETs and a zero-biased n-well to eliminate leakage currents. The FETs are operated using a constant current chosen to greatly reduce the FET's temperature sensitivity. The dose sensitivity of these p-FETs is about -2.6 mV/krad(Si) and the off-chip instrumentation resolves about 440 rad(Si)/b. When operated with a current at the temperature-independent point, it was discovered that the preirradiation output voltage is about -1.5 V, which depends only on design-independent silicon material parameters. The temperature sensitivity is less than 63 mu V/ degrees C over a 70 degrees C temperature range centered about the temperature-insensitive point. >

Semiconductor memory cell with SOI MOSFET

Abstract: A dynamic semiconductor memory cell 72 includes a trench 81 having an insulating film 74 that is used as a dielectric material of a memory capacitor, and a MOSFET 80 that is formed by a process including a step of transforming a polysilicon film 85 on the insulating film 74 into a single crystal. The adjacent trenches are insulated by the insulating film 74 and the MOSFET of the Semiconductor-on-Insulator structure is used to provide a structure which can prevent a leak current, does not need highly accurate mask positioning, and can provide a higher degree of integration. The SOI MOSFET is deposited on the same insulating film 74 that is used as a dielectric material in the capacitor. By keeping the surface of the insulating film 74 over the substrate 71 flush with that of the storage electrode layer 73 the SOI MOSFET can be formed without a contact opening step for the source 76.

Method for reducing on resistance and improving current characteristics of a MOSFET

Abstract: Construction and operation method for lightly doped drain MOSFET that has low or minimum drift on-state resistance and maintains high voltage blocking in the off-state. Temperature sensitivity of the electrical properties of the MOSFET are also reduced relative to MOSFETs produced by processes such as SIPOS. Voltage level shifting of p-channel and n-channel MOSFETs, produced according to the invention, relative to another voltage level is easily accomplished.

Integrated process for fabricating raised, source/drain, short-channel transistors

Abstract: Processes for fabrication of: an N-channel raised source/drain MOSFET transistor; an N-channel and P-channel raised source/drain MOSFET device; and an N-channel raised source/drain MOSFET in conjunction with a DRAM memory cell capacitor. The process deposits a layer of titanium nitride over the N-channel and P-channel source/drain areas which acts as a barrier to phosphorus or boron atom outdiffusion so that the junction doping levels remain low in the source/ drain areas, and N-channel and P-channel junctions will be shallow. The titanium nitride layer will serve as a dopant atom barrier in a capacitor storage node, an N-channel source/drain area, and a P-channel source/drain area.

Semiconductor memory device

Abstract: PURPOSE:To enable an SOI structure to be lessened in surface level difference, micronized, enhanced in density, and lessened in cell area. CONSTITUTION:A single-crystal silicon layer 4 formed by turning an amorphous silicon layer 3 into single crystal is laminated on the surface of a single-crystal silicon substrate 1 through intermediary of an insulating layer 2 to constitute an SOI structure, the source region 12 and the drain region 13 of an N-channel MOSFET 5 are formed by use of the single-crystal silicon layer 4, a capacitor 6 is formed in the insulating layer 2 vertically overlapping the N-channel MOSFET 5, the storage node 16 of the capacitor 6 is brought into contact with the side and the upside of the source region 12 of the N-channel MOSFET 5.

A new technique for measuring MOSFET inversion layer mobility

Abstract: An experimental technique for accurately determining both the inversion charge and the channel mobility mu of a MOSFET is presented. With this new technique, the inversion charge is measured as a function of the gate and drain voltages. This improvement allows the channel mobility to be extracted independent of drain voltage V/sub DS/ over a wide range of voltages (V/sub DS/=20-100 mV). The resulting mu (V/sub GS/) curves for different V/sub DS/ show no drastic mobility roll-off at V/sub GS/ near V/sub TH/. This suggests that the roll-off seen in the mobility data extracted using the split C-V method is probably due to inaccurate inversion charge measurements instead of Coulombic scattering. >

Current-regulated field emission cathodes for use in a flat panel display in which low-voltage row and column address signals control a much higher pixel activation voltage

Abstract: In a flat panel display in which low-voltage row and column address signals control a much higher pixel activation voltage by respectively gating at least one pair of series coupled MOSFETs to ground for each pixel, effective current regulation is achieved by placing a current-regulating resistor in series with each pair of the series-coupled MOSFETs. The resistor is coupled directly to ground and to the source of the MOSFET furthest from the emitter node. By coupling the current-regulating resistor directly to the ground bus, stable current values are achieved over a wide range of cathode voltages.

Method of manufacturing semiconductor device provided with capacitor and resistor

Abstract: A semiconductor integrated circuit including a MOSFET having a polycide gate structure, a resistor and a capacitor thereon is manufactured. Polycrystalline silicon film and a dielectric film are consecutively deposited. After processes of patterning and etching the dielectric film, the remaining dielectric films are used as a etching protection mask for the resistor and a capacitor insulating film for the capacitor. Then, a refractory metal silicide for a polycide gate is uniformly deposited over the remaining dielectric films. Then, the refractory metal silicide and polycrystalline silicon are consecutively etched over a patterned resist and the remaining dielectric films to simultaneously form the polycide gate, resistor and capacitor. Thus, a resistor having a precise resistance value is manufactured in a MOSFET device having a polycide gate without excessive steps.

The current-carrying corner inherent to trench isolation

Abstract: It is shown how the characteristics of the corner MOSFET inherent to trench isolation can be extracted from hardware measurements and how the corner device must be taken into account when extracting MOSFET channel characteristics. For NFETs it is found that the corner's threshold voltage, substrate sensitivity, and sensitivity to well doping are all smaller than the channel's. The results imply that for low-standby-power logic applications requiring high performance, it may become necessary to locally control the well doping at the corner. However, the corner's reduced substrate sensitivity and width independence can provide a significant advantage in a DRAM cell. >

Analytical modeling of threshold voltages in p-channel Si/SiGe/Si MOS structures

Abstract: An analytical model for the threshold voltages in a Si/SiGe/Si MOS structure is presented. It offers very good accuracy as compared to results of one- and two-dimensional numerical simulations. It is shown that short-channel effects lower the threshold voltage of the SiGe channel and increase the threshold voltage for parasitic conduction in the Si-cap layer. The model can serve as a useful tool for p-channel Si/SiGe/Si MOSFET design.

Differential analog memory cell and method for adjusting same

Abstract: A differential analog memory cell provides output signals governed by precisely adjustable voltage levels having minimal drift. The memory cell comprises a pair of differentially connected floating gate MOSFETs, each MOSFET having its source connected to a common current source and its drain connected to one leg of a current mirror. The floating gate of each MOSFET is connected to one electrode of a tunneling capacitor and one electrode of a coupling capacitor. Voltages applied to the other electrode of the tunneling capacitor inject charges onto the corresponding floating gate, the voltage of which is determined by the size of the coupling capacitor. Output voltages taken from the drains of the floating gate MOSFETs can be precisely adjusted up or down by applying single polarity voltage pulses to one or the other injector nodes.

Demonstration of the potential of accumulation-mode MOS transistors on SOI substrates for high-temperature operation (150-300 degrees C)

Abstract: Measurements of accumulation-mode (AM) MOS SOI transistors in the 150-300 degrees C temperature range are reported and discussed. The increases of the threshold voltage shift and off leakage current with temperature of these SOI p-MOSFETs are observed to be much smaller than their bulk equivalents. Simple models are presented to support the experimental data. >

Circuit design guidelines for n-channel MOSFET hot carrier robustness

Abstract: Reviews present understanding of the AC stress effect in n-MOSFETs, defining and parameterizing the AC stress model. The authors incorporate the AC hot-carrier model into a circuit-level hot-carrier reliability simulator, ADHOC, that works in concert with SPICE. Sources of on-chip voltage excursions above the nominal value of the power supply V/sub dd/ are explored, and this information is used to develop a set of design guidelines at the transistor level. The hot-carrier reliability of a broad class of basic circuit building blocks is then simulated and used as the basis for a comprehensive set of design guidelines at the transistor and circuit levels. >

Method of fabricating a silicon carbide vertical MOSFET and device

Abstract: A silicon carbide vertical MOSFET formed on a silicon carbide substrate with portions of epitaxial layers defining the various transistor electrodes, rather than defining the electrodes with implants and diffusion. An opening is formed in some of the epitaxial layers and a conductive layer is formed therein to electrically connect a drain contact on the rear of the substrate to the components on the front of the substrate.

Fabrication of a Si1-xGex Channel Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) Containing High Ge Fraction Layer by Low-Pressure Chemical Vapor Deposition

Abstract: A method for growing the high-quality strained epitaxial heterostructure of Si/Si1-xGex/Si by low-pressure chemical vapor deposition (CVD) and the fabrication of Si1-xGex-channel metal-oxide-semiconductor field-effect transistors (MOSFET's) with a high Ge fraction layer have been investigated. It is found that lowering of the deposition temperature of the Si1-xGex and Si capping layers is necessary with increasing Ge fraction in order to prevent island growth of the layers. With the use of the optimized fabrication process, Si/Si1-xGex/Si heterostructures with flat surfaces and interfaces were realized, and a high-performance Si0.5Ge0.5-channel MOSFET has been achieved with a large mobility enhancement of about 70% at 300 K and over 150% at 77 K compared with that of a MOSFET without a Si1-xGex channel.

Effects of total-dose irradiation on gate-all-around (GAA) devices

Abstract: The response of gate-all-around (GAA) MOS transistors to dose irradiation is quite different from that observed on other types of silicon-on-insulator (SOI) MOSFETs. In regular SOI MOSFETs, edge leakage increases substantially faster than the main transistor leakage upon creation of oxide charges due to the irradiation. The GAA MOSFET behaves in the opposite way; the shift of edge threshold voltage upon creation of charges in the oxide is smaller than that of the main transistor. As a result, a kink develops in the subthreshold characteristics of regular SOI MOSFETs upon irradiation, while the original subthreshold kink of GAA devices disappears when the device is irradiated. >

Power MOSFET with overcurrent and over-temperature protection

Abstract: A power integrated circuit is pin-compatible with a three-terminal power MOSFET and contains integrated circuits to turn off the device in the event of an overcurrent or an over-temperature condition. Control power voltage V cc is applied through a first MOSFET connected between the gate pin and the gate electrode of the power device. A second control MOSFET is connected across the power device gate and source electrodes. The first control MOSFET is turned off and the second control MOSFET is turned on in response to a fault condition. The turn off of the first MOSFET limits the current sinked by the gate pin. A novel boot strap circuit is disclosed which permits the use of all N channel MOSFETs with an N channel power device, and a novel trimmable temperature shutdown circuit is provided. An integrated bipolar transistor is also integrated into the chip to prevent conduction of the P well/N epi diode formed in the device substrate.

Real-time reconfigurable logic circuits using neuron MOS transistors

Abstract: A highly-flexible real-time-reconfigurable logic circuit implemented using a regular CMOS process is presented. The circuit, called soft-hardware logic (SHL), can alter its logic function (e.g. AND, OR, NAND, NOR, Exclusive OR, Exclusive NOR) in real time according to external control signals with no hardware modification. The circuit is one application of the neuron MOSFET (neuMOS or vMOS), a multiple-input functional MOS transistor simulating the function of biological neurons by a single device. The concept has been verified by experiments using test circuits fabricated by a standard double-polysilicon CMOS process. Details on the operational principle of the SHL circuit as well as design techniques are presented. One extension of this vMOS concept is a dynamic data-matching circuit in which rules for data matching are time-variable. Circuit operation has been verified by experiments. >

Impact of polysilicon depletion in thin oxide MOS technology

Abstract: Accurate characterization of thin oxide conduction current, breakdown, and MOSFET current require an accounting for the voltage drop due to the depletion of the polysilicon gate. The reduction of oxide thickness and polysilicon doping ascerbate this effect. Scaled n+/p+ dual gate CMOS technology incorporates both these trends, due to process integration constraints which limit the concentration of active dopants in polysilicon. The authors investigate effects of polysilicon depletion on the thin oxide MOS system. >