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Showing papers on "p–n junction published in 1993"


Journal ArticleDOI
TL;DR: In this paper, the fabrication technology and properties of a light-emitting device including a porous pn junction are presented, employing the selective formation of different kinds of porous silicon substructures caused by the doping level and the illumination during anodization.
Abstract: The fabrication technology and the properties of a light‐emitting device including a porous pn junction are presented. We employ the selective formation of different kinds of porous silicon substructures caused by the doping level and the illumination during anodization. The device has a nanoporous light‐emitting n layer between a mesoporous p+‐doped capping layer and the macroporous n substrate. The pn junction formed in this way has strong rectifying characteristics. It shows bright red‐orange light emission under forward bias. Compared to simple metal‐porous silicon devices, the structure has an increased quantum efficiency (factor 10–100).

146 citations


Journal ArticleDOI
TL;DR: In this paper, the nature of recombination centers in thin-film GaN diodes has been investigated and it was shown that both metal insulator-semiconductor and pn junction electroluminescence have been observed in thinfilm, metalorganic chemical vapor deposition-grown GaN Diodes thermally annealed in N2.
Abstract: Both metal‐insulator‐semiconductor and p‐n junction electroluminescence have been observed in thin‐film, metalorganic chemical vapor deposition‐grown GaN diodes thermally annealed in N2. UV radiation, peaking near 380 nm, is emitted when electrons are injected from the undoped, n‐type material into the Mg‐doped, p‐type GaN. Violet light, peaking near 430 nm, is obtained by injecting electrons into p‐type material from either n‐type material or non‐ohmic metal contacts. The present results support and extend earlier interpretations of the nature of the recombination centers in GaN.

132 citations


Journal ArticleDOI
TL;DR: In this paper, the authors examined optical absorption processes for applications of infrared lasers to the simulation of single-particle effects in silicon and GaAs, which require that the laser is focused to a small area on the device surface.
Abstract: The author examines optical absorption processes for applications of infrared lasers to the simulation of single-particle effects in silicon and GaAs, which require that the laser is focused to a small area on the device surface. The resulting charge generation is compared with charge generation from heavy ions. Charge funneling is reduced in silicon structures because of the lower charge density unless the LET (linear energy transfer) is above a threshold value. In both materials, the effective LET of a laser is inherently nonlinear because of nonlinear absorption at high intensities. These factors limit quantitative comparisons between lasers and heavy ions, and are increasingly important as devices are scaled to smaller dimensions. >

98 citations


Journal ArticleDOI
TL;DR: In this paper, the application of thermal, coevaporative doping with Sb and elemental B during Si molecular beam epitaxy at growth temperatures below ≊300 °C is discussed.
Abstract: Two‐dimensional doping sheets (‘‘δ doping’’) are integral parts of many novel semiconductor device concepts. Deep submicron design rules require junction depths significantly below 100 nm. This level of control is difficult to achieve with ion implantation. We discuss the application of thermal, coevaporative doping with Sb and elemental B during Si molecular beam epitaxy at growth temperatures below ≊300 °C to this problem. We show that it is possible to create structures with very high doping levels, yet with very sharp doping transitions. Delta‐doping spikes with a full width at half maximum of <2.7 nm and <4.0 nm have been obtained by secondary‐ion mass spectrometry for Sb and B, respectively, with corresponding up‐slopes of 2.5 and 0.94 nm/decade. Homogeneously doped films show full activation up to NSb≊6×1020 cm−3 and NB≳1×1021 cm−3. Mobilities agree with bulk values at corresponding concentrations. Mesa‐isolated pn junctions exhibit ideality factors of 1.05.

84 citations


Journal ArticleDOI
TL;DR: The technique has been extended to measurements down to 77 K and the simultaneous measurement of the minority‐carrier electron mobility utilizing open‐circuit voltage decay measurements.
Abstract: A considerable improvement in the accuracy of the measurement of the intrinsic carrier concentration in silicon near room temperature has recently been reported. This was achieved by the accurate analysis of minority‐carrier current flow in specially fabricated p‐n junction devices. In this paper this technique has been extended to measurements down to 77 K. A further improvement of the technique has been the simultaneous measurement of the minority‐carrier electron mobility utilizing open‐circuit voltage decay measurements.

83 citations


Patent
30 Nov 1993
TL;DR: In this paper, a semiconductor light-emitting device includes a plurality of semiconductor rods, each of which has a pn junction, and the plurality of rods are arranged at a distance substantially equal to an integer multiple of the wavelength of light emitted from the semiconductor rod.
Abstract: A semiconductor light-emitting device includes a plurality of semiconductor rods, each of which has a pn junction. The semiconductor rods are formed on a semiconductor substrate such that the plurality of semiconductor rods are arranged at a distance substantially equal to an integer multiple of the wavelength of light emitted from the semiconductor rod. With such devices, various novel optical devices such as a micro-cavity laser of which the threshold current is extremely small and a coherent light-emitting device having no threshold value can be realized.

82 citations


Journal ArticleDOI
TL;DR: In this article, the authors reviewed the progress of the technique and understanding of the mechanism for heteroepitaxial growth of nitride films on highly mismatched substrate (HGHMS) which was mainly developed by us.

81 citations


Patent
05 May 1993
TL;DR: In this paper, the reverse conducting function of an insulated gate bipolar transistor has been shown to have low operating resistance, a large reverse current can be passed, there is no increase in on-resistance, and the turn-off time can be shortened.
Abstract: An insulated gate bipolar transistor has a reverse conducting function built therein. A semiconductor layer of a first conduction type is formed on the side of a drain, a semiconductor layer of a second conduction type for causing conductivity modulation upon carrier injection is formed on the semiconductor layer of the first conduction type, a semiconductor layer of the second conduction type for taking out a reverse conducting current opposite in direction to a drain current is formed in the semiconductor layer of the second conduction type which is electrically connected to a drain electrode, and a semiconductor layer of the second conduction type is formed at or in the vicinity of a pn junction, through which carriers are given and received to cause conductivity modulation, with a high impurity concentration resulting in a path for the reverse conducting current into a pattern not impeding the passage of the carriers. Therefore, the built-in reverse conducting function has a low operating resistance, a large reverse current can be passed, there is no increase in on-resistance, and the turn-off time can be shortened.

75 citations


Journal ArticleDOI
TL;DR: In this paper, focused ion beam Ga+ implantation through Ti metal (ITM) and TiSi2 (ITS) layers, followed by rapid thermal annealing (RTA), has been investigated for application in self-aligned silicide technology.
Abstract: Focused ion beam Ga+ implantation through Ti metal (ITM) and TiSi2 (ITS) layers, followed by rapid thermal annealing (RTA), has been investigated for application in self‐aligned silicide technology. The Ga+ energy was varied from 25 to 50 keV at doses of 1×1013 and 1×1015 cm−2 followed by RTA at 600 °C for 30 s. Depth profiles of the Ga implants were obtained by performing secondary‐ion mass spectrometry. It was observed that higher‐energy and higher‐dose implants yielded good quality p+‐n junction characteristics. Diodes were fabricated to obtain the electrical properties of these silicided junctions. At higher implant energies (≥40 keV) and all doses, I‐V characteristics of ITS diodes showed 100 times lower leakage currents (Ir) than ITM diodes. For low‐energy (<40 keV)/high‐dose implantation the ITS diodes showed a slight improvement in Ir over the ITM diodes, whereas for low‐energy/low‐dose implantation the same Ir was observed.

53 citations


Patent
20 Jul 1993
TL;DR: A bottom-incidence type photo-sensing device has a pn junction, formed by selectively providing a first region of a second conductivity type in a portion of a semiconductive layer as discussed by the authors.
Abstract: A bottom-incidence type photo-sensing device has a pn junction, as a photo-sensing region, formed by selectively providing a first region of a second conductivity type in a portion of a semiconductive layer of a first conductivity type. The first region is surrounded by a second region of the second conductivity type formed in the semiconductive layer, and the second region is of the same or larger depth as or that of the first region. Even when light is directed to outside of the photo-sensing region, extra charges generated therein are absorbed by the second region and the flow of extra charges into the photo-sensing region is prevented.

46 citations


Journal ArticleDOI
TL;DR: In this article, a new type of light-emitting diode based on a porous silicon and microcrystalline silicon carbide pn junction was fabricated, and the visible light emission from 580 to 820 nm with a peak of 700 nm was observed at forward bias voltages larger than 18 V.
Abstract: We have fabricated a new type of light‐emitting diode based on a porous silicon and microcrystalline silicon carbide pn junction. The visible light emission from 580 to 820 nm with a peak of 700 nm was observed at forward bias voltages larger than 18 V, and the emission was quite uniform over an area of 1 cm2.

Journal ArticleDOI
TL;DR: In this article, a model for the p-n conversion during ion milling is discussed and the electron concentration in the n-type layer is of the order of 1015 cm-3 and is nearly constant from the surface to the p n junction.
Abstract: Thick n-type layers near the surface of p-Hg1-xCdxTe produced as a result of low energy ion milling have been investigated. EBIC measurements of cleaved cross sections show the depth and shape or the p-n junction under the surface of (HgCd)Te. An analysis of the n-type layers by differential Hall effect measurements is reported. It was found that the electron concentration in the n-type layer is of the order of 1015 cm-3 and is nearly constant from the surface to the p-n junction. A diminishing density of etch pits was found on the surfaces influenced by ion milling. A model for the p-n conversion during ion milling is discussed.

Journal ArticleDOI
TL;DR: In this article, annealing at 1060 degrees C for 10 s is used to create an amorphous Si layer to retard B channeling and diffusion, and then BF/sub 3/ is implanted.
Abstract: Plasma immersion ion implantation (PIII) is an efficient method for fabricating high-quality p/sup +//n diodes with junction depths below 100 nm. SiF/sub 4/ is implanted to create an amorphous Si layer to retard B channeling and diffusion, and then BF/sub 3/ is implanted. Ultrashallow p/sup +//n junctions are formed by annealing at 1060 degrees C for 10 s. With the shallow implants, no extended defects are observed in device or peripheral areas due to rapid outdiffusion of fluorine. Diode electrical characteristics yield forward ideality factor of 1.05-1.06 and leakage current density below 2 nA/cm/sup 2/ in the diode bulk. Minority-carrier lifetime below the junction is greater than 250 mu s. >

Patent
Richard M. Swanson1
29 Mar 1993
TL;DR: In this article, a porous emitter is provided which has high saturation current to limit injected charge when the device is conducting and a lightly doped region abutting a contact on the surface of the device to regulate minority carrier injection under forward bias.
Abstract: In a semiconductor P/N junction device, a porous emitter is provided which has high saturation current to limit injected charge when the device is conducting The porous emitter includes a lightly doped region abutting a contact on the surface of the device to regulate minority carrier injection under forward bias and shield the contact from stand-off field when the device is not conducting One or more heavily doped regions are provided in the first region to provide low contact resistance for the flow of majority carriers into the emitter

Patent
10 Dec 1993
TL;DR: In this article, an inexpensive, robust concrete solar cell comprises a photovoltaic material embedded in and extending beyond the major surfaces (16 and 18) of a matrix layer, which typically comprises a high strength, cementitious material, such as a macrodefect free cement.
Abstract: An inexpensive, robust concrete solar cell (10) comprises a photovoltaic material embedded in and extending beyond the major surfaces (16 and 18) of a matrix layer (14). The matrix layer typically comprises a high strength, cementitious material, such as a macrodefect free cement. The photovoltaic material comprises particles (12) of high-resistivity single crystal silicon, typically ball milled from ingot sections unsuitable for slicing into silicon wafers. The ingot sections include unprecipitated dissolved oxygen that is electrically activated by a low temperature annealing process to produce n-type silicon, even in silicon crystals that include a p-type dopant. An aluminum sheet (28), positioned on the backside of the matrix layer, is briefly melted together with the silicon particles to produce a p-type aluminum-doped silicon region (22) that forms a pn junction with the n-type region (24) of the particle. The aluminum sheet also provides the electrical contact to the p-type regions. The front surface of the matrix layer, from which the n-portion of the silicon particle protrudes, is covered with a translucent indium tin oxide conductive layer (30) that provides electrical contacts to the n-portion of the pn junction and digitated electrode (32) for conducting current off the cell. A voltage is generated between the two conductive layers when light incident on the photovoltaic particle through the indium tin oxide conductive layer creates charge carriers.

Patent
25 Aug 1993
TL;DR: In this paper, a semiconductor light emitting element comprising a lower electrode on its back, a pn junction, a first light reflecting layer disposed between the substrate and the pn-junction, an upper electrode, and a second light reflecting mechanism disposed between pn and the upper electrode was proposed.
Abstract: A semiconductor light emitting element comprising a semiconductor substrate having a lower electrode on its back, a pn junction, a first light reflecting layer disposed between the substrate and the pn junction, an upper electrode, and a second light reflecting layer disposed between the pn junction and the upper electrode, the second light reflecting layer being capable of substantially reflecting the light heading toward the upper electrode, which preferably has, between the pn junction and the second light reflecting layer, a semiconductor layer having a wider bandgap than that of a light emitting layer formed by said pn junction. The semiconductor light emitting element of the invention is advantageous in that the light absorption in the upper electrode can be inhibited to permit efficient output of the light heading toward the upper electrode from the element, and luminance can be greatly increased by the effective output of the light from the element.

Journal ArticleDOI
TL;DR: In this paper, two models, recombination and bremsstrahlung models, are proposed for the interpretation of visible light emission from reverse-biased semiconductor junctions under breakdown conditions.
Abstract: There are two models, recombination and bremsstrahlung models, proposed for the interpretation of visible light emission from reverse-biased semiconductor junctions under breakdown conditions. The emission spectra are calculated on the basis of these two models and compared with the published experimental results on Si and Ge p-n junctions. Experimental spectra can be interpreted well using the model of recombination between conduction-band electrons and valence-band holes. The spectra calculated on the basis of the bremsstrahlung model cannot be fitted to the experimental ones.

Journal ArticleDOI
TL;DR: In this paper, the authors reported a recent experiment on resonant interband tunneling (RIT) diodes and the measured room temperature peak-to-valley (P/V) current ratio of 104:1 which represents the highest P/V ratio ever reported in any tunneling device.
Abstract: This letter reports a recent experiment on resonant interband tunneling (RIT) diodes and the measured room temperature peak‐to‐valley (P/V) current ratio of 104:1 which represents the highest P/V ratio ever reported in any tunneling device. The RIT diode studied in this work consists of an InGaAs/InAlAs double‐quantum well system embedded in a pn junction structure grown on InP.

Journal ArticleDOI
TL;DR: In this article, the influence of different diffusion lengths at both sides and the angle between the GB and the surface is discussed and the local current voltage characteristics of the GB are obtained from which change of the local barrier height with increasing injection level can be deduced.
Abstract: Grain boundary‐electron beam induced current (GB‐EBIC) is an alternative EBIC geometry without a Schottky contact or pn junction but with ohmic contacts on either side of a GB. The GB itself acts as a charge collecting plane. We developed this EBIC mode both experimentally and theoretically. We calculated the current profiles with the diffusion length and the recombination velocities of the GB and the surface as parameters by solving the three‐dimensional diffusion problem. The influence of different diffusion lengths at both sides and the angle between GB and surface is discussed. By variation of the injection level and application of an external bias local current voltage characteristics of the GB are obtained from which change of the local barrier height with increasing injection level can be deduced. We can describe the measured recombination behavior by an electronic GB model with a double depletion layer and deep interface states in a detailed balance approach. We applied this EBIC mode to grain bou...


Patent
25 Jan 1993
TL;DR: In this paper, a method for forming a p-n junction in silicon carbide includes the steps of masking an area on the face of the monocrystalline substrate and then directing electrically inactive ions to the masked area so that an amorphous region in the substrate is formed.
Abstract: A method for forming a p-n junction in silicon carbide includes the steps of amorphizing a portion of a monocrystalline silicon carbide substrate, implanting dopant ions into the amorphous portion of the substrate and then recrystallizing the amorphous portion to thereby form a substantially monocrystalline region including the dopant ions. In particular, the amorphizing step includes the steps of masking an area on the face of the monocrystalline silicon carbide substrate and then directing electrically inactive ions to the masked area so that an amorphous region in the substrate is formed. Accordingly, the amorphous region has sidewalls extending to the face that are substantially orthogonal to the bottom edge of the amorphous region. Once the amorphized region is defined, electrically active dopant ions are implanted into the amorphous region. The dopant ions are then diffused into the amorphous region and become uniformly distributed. Next, the doped amorphized region is recrystallized to obtain a substantially monocrystalline doped region. If the region surrounding the recrystallized region are of opposite conductivity type, a vertically walled p-n junction is formed.

Journal ArticleDOI
TL;DR: In this article, a method for preparing doped specimens of amorphous germanium and silicon by rf sputtering was described, and conductivity and thermoelectric power measurements were taken to demonstrate that doping has been achieved.

Journal ArticleDOI
E. Flack, W. Gerlach, J. Korec1
TL;DR: In this article, the influence of a high-voltage interconnection on the blocking capability of a resurf diode is determined by solving the 2-D Poisson equation, and two different methods are discussed.
Abstract: The influence of a high-voltage interconnection onto the blocking capability of a resurf diode is determined by solving the 2-D Poisson equation. By adding a metal interconnection which crosses the space-charge region, the breakdown voltage is reduced, depending on the distance between the interconnection and the semiconductor surface. If the distance is 5 mu m, the breakdown voltage is decreased 38%, but if the distance is as low as 3 mu m, the breakdown voltage is decreased by 54%. To compensate for the effect of the interconnection two different methods are discussed. By optimizing the doping concentration of the p/sup -/layer in front of the p-n junction the influence of the interconnection can be reduced to 18% and 37%, respectively. The second method uses floating metal rings positioned in the oxide film between the semiconductor and the interconnection. If the rings are optimally positioned, the influence of the interconnection can be reduced from 54% to only 16%. It is shown that a variation of the lateral gap between the metal rings influences the shielding effectiveness. >

Journal ArticleDOI
TL;DR: In this article, the fabrication and initial electrical characterization of greatly improved 3C-SiC p-n junction diodes are reported, which demonstrate rectification to -200 V at room temperature, representing a fourfold improvement in reported 3CSiC diode blocking voltage.
Abstract: The fabrication and initial electrical characterization of greatly improved 3C-SiC ( beta -SiC) p-n junction diodes are reported. These diodes, which were grown on commercially available 6H-SiC ( alpha -SiC) substrates by chemical vapor deposition, demonstrate rectification to -200 V at room temperature, representing a fourfold improvement in reported 3C-SiC diode blocking voltage. The reverse leakage currents and saturation current densities measured on these diodes also show significant improvement compared to previously reported 3C-SiC p-n junction diodes. When placed under sufficient forward bias, the diodes emit significantly bright green-yellow light. These results should lead to substantial advancements in 3C-SiC transistor performance. >

Patent
Masao Yamada1, Motoo Nakano1, George J. Collins1, Tetsuro Tamura1, Akira Takazawa1 
28 Apr 1993
TL;DR: In this article, an Si or SiC semiconductor layer is subjected to anodic oxidization in an HF solution to form a porous semiconductor layers, which are then dipped in pure water to shorten reaction time and help bubbles separate from the surface of the porous region.
Abstract: An Si or SiC semiconductor layer is subjected to anodic oxidization in an HF solution to form a porous semiconductor layer. Without drying the porous semiconductor layer, it is then dipped in pure water. Ultrasonic waves applied to the pure water shorten the reaction time and help bubbles separate from the surface of the porous region. The porous semiconductor layer is used for forming a pn junction, and carriers are injected into the pn junction.

Patent
01 Jul 1993
TL;DR: In this paper, an integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region of a first conductivity type extending from a semiconductor top surface is described.
Abstract: An integrated edge structure for a high voltage semiconductor device comprising a PN junction represented by a diffused region of a first conductivity type extending from a semiconductor device top surface is described. The edge structure comprises a first, lightly doped ring of the first conductivity type obtained in a first, lightly doped epitaxial layer of a second conductivity type and surrounding said diffused region, and a second, lightly doped ring of the first conductivity type, comprising at least one portion superimposed on and merged with said first ring, obtained in a second, lightly doped epitaxial layer of the second conductivity type grown over the first epitaxial layer.

Journal ArticleDOI
TL;DR: In this article, the nanosecond thermal diffusion (NTD) method was used to incorporate and diffuse impurities in silicon wafers, and it has been applied to the fabrication of ultra-shallow diodes with ideality factors of 1.01-1.10.

Journal ArticleDOI
TL;DR: In this paper, a GaAs p−n tunnel diode with an InxGa1−xAs layer (Lz∼100 A) in the barrier region to reduce the energy gap and increase the tunneling probability without sacrificing the high injection barrier and voltage of GaAs.
Abstract: Data are presented showing that a GaAs p‐n tunnel diode can be modified, and improved, with the introduction of an InxGa1−xAs layer (Lz∼100 A) in the barrier region to reduce the energy gap (and carrier mass) and increase the tunneling probability without sacrificing the high injection barrier and voltage of GaAs. Peak tunnel current densities in the range (1–1.5)×103 A/cm2 are obtained, with peak‐to‐valley current ratios of ∼20:1 and voltage ‘‘swings’’ from peak tunnel current to equal injection current of ≳1 V (≤1 V for GaAs). The C‐doped GaAs(p+)‐InGaAs(n+)‐GaAs(n+) diodes are grown by metalorganic chemical vapor deposition and are compared to GaAs tunnel diodes fabricated by the usual alloy process (i.e., local liquid phase epitaxy).

Patent
14 May 1993
TL;DR: In this paper, a single quantum well II-VI laser diode without semiconductor cladding layers includes a pn junction formed by overlaying light-guiding layers (14, 16) of p-type and n-type ZnSe on an n type GaAs substrate.
Abstract: A single quantum well II-VI laser diode without semiconductor cladding layers includes a pn junction formed by overlaying light-guiding layers (14, 16) of p-type and n-type ZnSe on an n-type GaAs substrate. A CdSe/ZnSe short-period strained-layer superlattice single quantum well active layer (12) is positioned between the guiding layers. An Au electrode (24) overlays the p-type guiding layer opposite the single quantum well active layer. The guiding layers have thicknesses which enable the substrate and Au electrode to confine the light beam generated by the device within the active layer and the guiding layers.

Patent
28 Apr 1993
TL;DR: In this article, a cold cathode electron sourcing arrangement where a negative electron affinity material such as p-type diamond is disposed adjacent to a p-n junction in order that electron charge carriers originating in the p n junction may be caused to flood the p type diamond and increase its electrical conductivity and also provide a source for high current flow free electrons repelled from the surface of the diamond material.
Abstract: A cold cathode electron sourcing arrangement wherein a negative electron affinity material such as p-type diamond is disposed adjacent a p-n junction in order that electron charge carriers originating in the p-n junction may be caused to flood the p-type diamond and increase its electrical conductivity and also provide a source for high current flow free electrons repelled from the surface of the diamond material. Theoretical consideration of the high current electron source is also disclosed. Use of the electron source in cathode ray tubes and other electron based apparatus is also included. The disclosed electron sourcing is distinguished from that of previously known n-type diamond.