Showing papers on "Parasitic capacitance published in 1995"

Cmos integrated microsensor with a precision measurement circuit

Abstract: Improved microsensors are provided by combining surface micromachined substrates, including integrated CMOS circuitry, together with bulk micromachined wafer bonded substrates which include at least part of a microelectromechanical sensing element. In the case of an accelerometer, the proof mass is included within the wafer bonded bulk machined substrate, which is bonded to the CMOS surface machine substrate, which has corresponding etch pits defined therein over which the wafer bonded substrate is disposed, and in the case of accelerometer, the proof mass or thin film membranes in the case of other types of detectors such as acoustical detectors or infrared detectors. A differential sensor electrode is suspended over the etch pits so that the parasitic capacitance of the substrate is removed from the capacitance sensor, or in the case of a infrared sensor, to provide a low thermal conductance cavity under the pyroelectric refractory thin film. Where a membrane suspended electrode is utilized over an etch pit, one or more apertures are defined therethrough to avoid squeeze film damping. Accelerometers built according to the methodology are provided with a nulling feedback voltage to maintain the switch DC voltage across sensing capacitors in a null condition and to maintain high sensitivity without requiring either a precision transformer or regulated power sources in the capacitance bridge of the accelerometer.

Planar microwave and millimeter-wave lumped elements and coupled-line filters using micro-machining techniques

Abstract: Planar microwave and millimeter-wave inductors and capacitors have been fabricated on high-resistivity silicon substrates using micro-machining techniques The inductors and capacitors are suspended on a thin dielectric membrane to reduce the parasitic capacitance to ground The resonant frequencies of a 12 nH and a 17-nH inductor have been increased from 22 GHz and 17 GHz to around 70 GHz and 50 GHz, respectively We also report on the design and measurement of a new class of stripline filters suspended on a thin dielectric membrane Interdigitated filters with 43% and 5% bandwidth have been fabricated and exhibit a port-to-port 07 dB and 20 dB loss, respectively, at 14-15 GHz The micro-machining fabrication technique can be used with silicon and GaAs substrates in microstrip or coplanar-waveguide configurations to result in planar low-loss lumped elements and filters suitable for monolithic integration or surface mount devices up to 100 GHz >

Capacitive fingerprint acquisition sensor

Abstract: An apparatus for detecting topographic variations on an object such as a finger includes an array of sensing elements disposed on a substrate which each have a parasitic capacitance. An insulating receiving surface is disposed over the array of sensing elements and is adapted to receive the object such that a sensing element and a portion of the object located thereabove creates a measurable change in capacitance with respect to the parasitic capacitance. An electronic circuit is coupled to the array of sensing elements for measuring the measurable change in capacitance.

A practical approach for magnetic core-loss characterization

Abstract: A practical approach for magnetic core-loss characterization up to a few megahertz is presented. An error analysis is for the first time performed, revealing that corrections are needed to compensate for errors introduced by the extra phase shift inherent in a measurement setup, and by shunt parasitic capacitance associated with an inductive device under test. A simple technique is then proposed to control the error so as to satisfy prescribed tolerances. Extensive measurements done on a TDK PC40 core yield results which support the analysis. Several sample cores are then characterized at a few megahertz. >

Extraction of circuit models for substrate cross-talk

Abstract: An increasingly urgent topic for the realization of densely packed (mixed signal) integrated circuits is prevention of cross-talk via the substrate. This paper proposes a Boundary Element Method (BEM) for calculating an admittance matrix for the substrate in order to analyze the parasitic coupling during layout verification.In contrast with standard BE methods, we propose a Green's function which is specific to the domain and the problem. This allows minimal discretization and a direct extraction of circuit models for the cross-talk. The extraction can be combined with an efficient model reduction technique to obtain more simple, yet accurate models for the cross-talk. The complete extraction process has a linear time complexity and a constant memory usage. The method is fully implemented and integrated in an existing layout-to-circuit extractor.

New, zero voltage switching, high frequency boost converter topology for power factor correction

Abstract: This paper introduces a technique for combining zero-voltage-switching with boost converter technology to enable high frequency, high efficiency operation of the converter. The combination creates a new topology which is effective to meet the power factor correction and harmonic reduction requirements of new EMC standards. The unique topology provides limitation of the recovery current of the boost diode and uses the energy recovered from the reverse current to discharge the intrinsic and stray capacitance of the boost switch while transferring this recovered energy to the output. With the main switching losses removed, the frequency can be increased to reduce the size of the boost inductor while maintaining continuous conduction mode operation for improved input noise filtering.

Pulse shaping FM demodular with low noise where capacitor charge starts on input signal edge

Abstract: A receiver having, arranged in this order, an input section, an FM demodulator, to which a frequency-modulated input signal is applied, and an LF section, which FM demodulator includes a pulse shaper and a low-pass filter, the pulse shaper comprising a series arrangement of at least a load and a capacitance, the base-emitter junction of a transistor being arranged across the capacitance, and further including a switching device for charging and discharging the capacitance The pulse shaper generates a low-noise pulse in that charging of a capacitance is started upon an edge of the input signal The capacitance voltage is measured by a single transistor and when the transistor is turned on, the charging current of the capacitance is diverted via the transistor, so that the capacitance voltage is limited The capacitance is discharged upon a second edge, after which the cycle is repeated The output signal of the pulse shaper is a signal which varies with the current through the capacitance

SRAM cell with no PN junction between driver and load transistors and method of manufacturing the same

Abstract: SRAM memory cells is provided with high resistance to soft error and no parasitic capacitance due to PN junction. SRAM memory cells comprises the load resister is a thin film transistor having a same conductive type as that of the driver transistor.

Capacitance-sensitive switch and switch array

Abstract: A capacitance-sensitive switch unit (10) including a capacitive element (18) operable to produce an effective capacitance dependent upon the physical proximity of objects relative thereto, a first selector signal input (14) connected to the capacitive element (18) to enable a first input signal to charge the effective capacitance, a threshold signal producing circuit (35) connected to the capacitive element (18) for producing a threshold signal which is rendered active when the effective capacitance charges to a pre-defined potential, a switching circuit (33) for selectively connecting the capacitive element (18) to the treshold signal producing circuit (35) in response to a switching signal and a discharge control circuit (11) connected to the capacitive element (18), for selectively discharging the effective capacitance independently of the input signal, in response to a discharge signal. Also disclosed is a switch array (100) employing structure similar to the above.

Vibration damping system using active negative capacitance shunt circuit with piezoelectric reaction mass actuator

Abstract: Boring bar vibration damping is improved by a novel use of the electromechanical properties of the piezoelectric actuator material. A negative capacitance shunt circuit is provided in which a voltage-controlled voltage-source continuously simulates a negative capacitance that is substantially equal in magnitude but opposite in phase to the capacitance of the piezoelectric material. The negative capacitance is shunted across the piezoelectric device, effectively compensating for the capacitance of the device across a broad frequency band. The voltages generated in the piezoelectric element in response to mechanical deformation induced by broadband vibrations of the structure during damping operations, may then be completely resistively dissipated, thereby enhancing the mechanical damping.

A novel resonant snubber based soft-switching inverter

Abstract: A new soft-switching inverter has been developed to overcome overvoltage and overcurrent problems in the existing resonant link inverters This inverter employs a single auxiliary switch and a resonant inductor per phase to produce a zero voltage across the main switch so that the main switch can turn on at a lossless condition Both the auxiliary switch and the resonant inductor are operating at a fractional duty, and thus are small in size compared to the main inverter circuit components Although the resonance can be obtained with the use of the stray capacitance across the main switch, typical implementations require a small capacitor paralleling with the main switch to obtain nearly lossless turn-off This paper describes both three-phase and single-phase circuit configurations Operation modes in a complete zero-voltage switching cycle for the single-phase soft-switching inverter are described in detail with graphical explanation Because the zero voltage condition is predictable by the selected circuit components, the implementation of this inverter does not require any voltage or current sensors The circuit operation was first verified by a computer simulation and then further tested with a 1 kW power MOSFET based single-phase inverter Both simulation and experimental results are presented to show the superiority of the proposed soft-switching inverter >

Content-addressable-memory control circuit

Abstract: A timing control signal SR is made low to switch on a P-MOSFET and switch off an N-MOSFET, and with an N-MOSFET as a boundary, a voltage V MATCHI on the side of a NOT circuit of a match-line is pulled up to a power supply voltage V DD . During this, a comparison operation is done in a content addressable memory cell, and an N-MOSFET is switched on or off according to the result of comparison. Next, the control signal SR goes to a logic high level, so the P-MOSFET is switched off and the N-MOSFET is switched on. As a result, if the N-MOSFET is on, the voltages V MATCHI and V MATCH will be reduced to a ground level, but the through current is prevented because the P-MOSFET is off. If the N-MOSFET is off, the V MATCH will be pulled up to V DD -V tn (V tn is the threshold voltage of the N-MOSFET), the V MATCHI will be held to V DD by the NOT circuit and the P-MOSFET, and a signal representative of a result of comparison will be output from the NOT circuit. Also, by the interval of the N-MOSFET, the parasitic capacitance of the portion on the side of the content addressable memory cell of the match-line with the MOSFET as a boundary disappears from the portion on the side of the pull-up means from the portion on the side of the NOT circuit with the voltage drop element as a boundary, so the pull-up of the portion on the side of the NOT circuit with the MOSFET as a boundary becomes fast.

Method and apparatus for modeling capacitance in an integrated circuit

Abstract: According to the present embodiment, a method for calculating the parasitic capacitance in a semiconductor device is disclosed. According to the preferred method, a layout file containing the shapes of a semiconductor device is provided. The dimensions of the layout file are then adjusted to wafer dimensions so as reflect actual production devices. The shapes of the layout file are then partitioned into simpler shapes, typically abutted rectangles, called tiles. Each tile is then decomposed into overlap and fringe capacitance components, each component having a uniform capacitance environment with respect to its capacitance elements. The parasitic capacitance of the semiconductor device can thus be accurately computed, with an efficient use of resources. Additionally the preferred embodiment is easily adaptable to a wide range of technology types.

Method for making CMOS device having reduced parasitic capacitance

Abstract: A CMOS device having reduced parasitic junction capacitance and a process for fabrication of the device. The device includes an a portion (20') of an undoped epitaxial layer (20) vertically separating source and drain regions (52 and 53, 54 and 55) from buried layers (16, 18) formed in a semiconductor substrate (12). The undoped epitaxial layer (20) reduces the junction capacitance of the source and drain regions by providing an intrinsic silicon region physically separating regions of high dopant concentration from the source and drain regions. Additionally, MOS transistors fabricated in accordance with the invention have fully self-aligned channel regions extending from the upper surface (22) of the undoped epitaxial layer (20) to the buried layers (16, 18) residing in the semiconductor substrate (12).

120-GHz long-wavelength low-capacitance photodetector with an air-bridged coplanar metal waveguide

Abstract: We demonstrate a long-wavelength detector structure using an undercut mesa and an air-bridged coplanar metal waveguide to significantly reduce both the diode RC constant and the parasitic capacitance. Record electrical bandwidths of 120 GHz are demonstrated for long-wavelength photodetectors.

A four-electrode system for measurement of bilayer lipid membrane capacitance

Abstract: A four-electrode capacitance-to-period converter designed for capacitance measurements of bilayer lipid membranes is described. The capacitance measurement consists of cyclically charging and discharging the measured capacitance with a constant current, regarding its absolute value. The voltage of the studied capacitor is triangularly shaped. The cycle duration is proportional to the input capacitance. Capacitance measurement with a four-electrode system makes it possible to reduce considerably the errors caused by electrode and electrolyte impedance. It is possible to use high-resistance microelectrodes. The system makes it possible to measure the capacitance at an imposed polarization potential; the voltage oscillates about that value during the measurement. This makes it possible to measure the membrane capacitance as a function of polarization potential. An example is cited of using the capacitance-to-period converter in a computer-controlled measuring system.

The design of active floating positive and negative inductors in MMIC technology

Abstract: An original method for the determination of all possible inductive circuits as a function of the number of FET's used is described in this paper. The method is of general use in monolithic microwave integrated circuits. Circuits with large inductance, either positive or negative in value, can be obtained along with low loss or even negative resistance. >

Electronic circuit with operation self-control function

Abstract: An electronic circuit with an operation self-control function includes an electronic circuit body. A temperature sensor and a temperature-setting circuit detect the temperature of the electronic circuit body as an operating parameter indicative of an operating condition of the electronic circuit body, and a clock/peripheral circuit control circuit operates to restrict the operation of the electronic circuit body according to the detected temperature, to thereby restrain heat generation of the electronic circuit body.

Variable capacitor formed by multilayer circuit board

Abstract: A variable capacitor for a high frequency circuit of an electrical appliance includes a chip capacitor mounted on a multilayer circuit board and interdigital capacitors formed at inner layers of the circuit board. A wiring pattern for soldering the chip capacitor is connected with the interdigital capacitors via through holes formed in the circuit board. Capacitance select portions are cut so that the capacitance best-suited to the circuit is obtained. The through holes connected to the interdigital capacitors of the inner layer are selectively disconnected from the wiring pattern for soldering the chip capacitor, thereby obtaining a variable capacitor capable of absorbing fluctuations of the circuit for selecting the best-suited capacitance.

Low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries

Abstract: A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section and a slave section, is disclosed and claimed. The master section includes a master latch structure, a master coupling circuit which connects the master latch structure to one of two supply voltages, and an input coupling circuit for applying data to the flip-flop. The slave section includes a slave latch structure directly interposed between two supply voltages, and a slave coupling circuit which connects the slave latch structure to the master latch structure. The number of transistors required to realize the D flip-flop circuit implementation of the invention is minimized by enlarging the source areas of transistors in the input coupling circuit, which results in a large stray capacitance and insures optimum operation of the master latch. In addition, transistors in the slave latch structure have non-minimal gate lengths. Furthermore, a single clock signal is used to enable both master and slave sections. The ability to use a single clock signal without local regeneration coupled with minimizing the number of required components facilitates higher integrated circuit density and reduces power consumption.

Metal-oxide-semiconductor field-effect transistor and its method of fabrication

Abstract: The structural configuration of an improved submicron metal-oxide semiconductor field-effect transistor and the method of its fabrication are disclosed. A field oxidation procedure is employed to increase the thickness of the gate oxide layer at both of its ends. The result is decreased gate and drain overlapping region parasitic capacitance, as well as decreased gate-induced drain-leakage current, due to the reduction of the electric field intensity in the overlapping region at which the thickness is increased. The resulting metal-oxide semiconductor field-effect transistor, therefore, is provided with improved operating characteristics for use at high frequencies.

InP/InGaAs double-heterostructure bipolar transistors for high-speed ICs and OEICs

Abstract: This paper describes a novel collector structure for full-potential InGaAs (FPIGA) double-heterostructure bipolar transistors (DHBTs). This new structure not only ensures high-speed operation, high breakdown and low collector turn-on voltages, but also provides pin photodiode (PD) layers suitable for high-speed and high-sensitivity operations. The FPIGA DHBT collector structure is primarily composed of relatively thick undoped, thin p+- and thin n+-InGaAs layers, and a lightly doped N-InP layer. They form a potential notch at the InGaAs InP interface at a relatively long distance from the base-collector interface, which effectively suppresses the current blocking effects arising from the conduction band discontinuity at the InGaAs InP interface. The thin p+-InGaAs layer also raises the conduction band in the collector to enhance the ballistic transport of electrons. Breakdown voltage increases because the major part of the potential change at high collector bias occurs in the N-InP layer. The layer compatibility of both the high-performance DHBTs and high-speed PDs enables us to easily manufacture optoelectronic integrated circuits (OEICs). A 1.6 × 4.6-μm2 emitter FPIGA DHBT shows a current gain cutoff frequency, fT, of 160 GHz and a maximum oscillation frequency, fmax, 162 GHz. The fT value reaches 124 GHz at low VCE of 0.65 V owing to the suppressed electron blocking effect. A small FPIGA DHBT with a 0.6 × 1.6-μm2 emitter operates with 118 GHz fT and 148 GHz fmax at an IC as low as 1 mA. The breakdown voltages of the DHBTs are high enough for any high-speed IC applications. A photoreceiver OEIC comprising a pin PD and an amplifier implemented with the FPIGA DHBTs operates error free up to 10 Gbit/s for 1.55 μm wavelength NRZ signals. For electrical inputs, the amplifier provides a transimpedance of 47.2 dBΩ with 3 dB bandwidth of 23 GHz although it has a disadvantage of parasitic capacitance of the pin PD.

Method of extracting parasitic capacitance values from the physical design of an integrated circuit

Abstract: A method of extracting parasitic capacitance values from the physical design of an integrated circuit, and more particularly, to a method of extracting lateral coupling and fringing capacitance values from the physical design of an integrated circuit, wherein the integrated circuit comprises multiple layers of conductors, each conductor having one or more lateral edges. The method comprises the steps of identifying each conductor's one or more lateral edges; fragmenting the lateral edges of each conductor into edge fragments based on a number of conductors present in layers above and/or below a given lateral edge; identifying the edge fragments which are laterally adjacent to each edge fragment; computing one or more relationships between an edge fragment and each of its laterally adjacent edge fragments; retrieving parasitic capacitance data for each edge fragment; and using the retrieved parasitic capacitance data to compute one or more parasitic capacitance values for each edge fragment. Disadvantages of prior methods are overcome in that extracted lateral coupling capacitances are based on the presence of conductors running above and/or below a given lateral conductor edge, and fringing capacitances are based on the spacing between a given lateral conductor edge and a laterally adjacent conductor edge.

On-chip decoupling capacitor design to reduce switching-noise-induced instability in CMOS/SOI VLSI

Abstract: The supply noise from the packaging of CMOS/SOI circuits can cause performance degradation, reliability reduction and even loss of circuit functionality due to the device latch-up problem. By properly adding on-chip decoupling capacitors in the proximity of the circuitry, we can effectively alleviate the switching noise problem and improve the performance of CMOS/SOI circuits.

Liquid-crystal display device and driving method thereof

Abstract: The structure of pixel electrode constituting a pixel element of a liquid-crystal display device employing the capacitively coupling driving method and driving method for the device are described. The field of view angle at the main viewing direction is increased and the grayscale graduation reversal is eliminated through a procedure of sequentially increasing or decreasing, at each scanning busline, the value of compensating potential at a time when a potential being applied to the gate terminal of the switching element shifts from ON potential to OFF potential, to be applied on an adjacent scanning busline to which the storage capacitance is formed, by setting each of the values of storage capacitance ratio and parasitic capacitance ratio different through making each of the values of storage capacitance and parasitic capacitance formed between the plural pixel electrodes and respective switching elements within one pixel element different to each other.

Misfire detecting circuit for internal combustion engine

Abstract: There is provided a misfire detecting circuit for an internal combustion engine for detecting a misfire on the basis of the presence or absence of an ion current caused by combustion by applying a voltage to an ignition plug of the internal combustion engine, which circuit prevents malfunction caused by stray capacitance generated in the line up to the ignition plug and by the input impedance of the circuit. The misfire detecting circuit includes an ion current detection section which is formed of a diode for causing electric current to flow out from a capacitor, which diode is connected between the ground and the electrode on the low potential side of the capacitor which is charged by electric current at the time of ignition and charged to a predetermined voltage for detecting the ion current, and a current/voltage conversion section which is formed of a diode for causing electric current to flow out and of an operational amplifier whose inverting input is connected to the electrode on the low potential side of the capacitor and whose non-inverting input is connected to the ground.

Method of making an array of TFTs having reduced parasitic capacitance

Abstract: A thin film transistor (TFT) array in an active matrix liquid crystal display (AMLCD) including a centrally located round source electrode completely surrounded by a substantially annular or circular shaped drain electrode. The geometric design of the TFT of this invention provides for a thin film transistor having a reduced parasitic capacitance and decreased photosensitivity. The TFTs of this invention are located at the intersections of gate and drain lines of an active matrix LCD array thereby increasing the size of the pixel display openings of the matrix array.

Class E half-wave low d/spl nu//dt rectifier operating in a range of frequencies around resonance

Abstract: A Class E half-wave low d/spl nu//dt rectifier is analyzed; simulation and experimental results are given when it operates in a large range of frequencies around resonance. The diode parasitic capacitance is included in the parallel capacitance. The leads inductance and the isolation transformer leakage inductance (if any) are included in the series inductance. Simple and accurate modeling is thus possible. Equations describing the circuit operation are derived for the rectifier being driven by a sinusoidal voltage source. Theoretical, simulation and experimental results are in good agreement. >

Electronic circuit structure with aperture suspended component

Abstract: An electronic circuit structure having a reduced size includes a circuit substrate, an aperture extending through the circuit substrate, and an electronic component suspended within the aperture. The suspension of the electronic component within the aperture significantly reduces the profile of the overall electronic circuit structure. The aperture further enables electronic components to be mounted in a partially overlapping fashion to reduce the surface area of the electronic circuit structure. The electronic circuit structure can make use of standard FR-4, G-10, or ceramic circuit substrates or multilayer flex circuits, as well as electronic components in the form of standard leaded integrated circuit packages. The mounting of the electronic component within the aperture of the circuit substrate provides an advantage of assisting in heat dissipation. The incorporation of mesh-like voltage and ground planes can further aid in heat dissipation and provide electrical isolation and capacitive filtering. In addition, the electronic circuit structure facilitates high density packaging of several electronic structures, for example, in a stacked or radial configuration.

Ultrafast characterization of an in‐plane gate transistor integrated with photoconductive switches

Abstract: An in‐plane gate field‐effect transistor is characterized by ultrafast electro‐optic sampling. The transistor is monolithically integrated with photoconductive switches in coplanar waveguide and <0.5 ps measurement time resolution is achieved. The gate‐drain capacitance of the transistor is obtained as 1.8 fF at zero drain voltage from displacement current transients. The gate‐drain capacitance is dominated by parasitic capacitance and the intrinsic gate‐drain capacitance is estimated as less than 0.2 fF.