Showing papers on "Physical design published in 1990"

Combinatorial Algorithms for Integrated Circuit Layout

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The Olympus synthesis system

Abstract: A description is given of the Olympus synthesis system for digital design, a vertically integrated set of tools for multilevel synthesis, technology mapping, and simulation. The system includes behavioral, structural, and logic synthesis tools, and provides technology mapping and simulation. Since it is targeted for semicustom implementations, its output is in terms of gate netlists. Instead of supporting placement and routing tools, Olympus provides an interface to standard physical design tools. The system supports the synthesis of ASICs (application specific integrated circuits) from behavioral descriptions written in a hardware description language called HardwareC. Two internal models represent the hardware at different levels of abstraction and provide a way to pass design information among different tools. Olympus has been used to design three ASIC chips, and has been tested against benchmark circuits for high-level and logic synthesis. >

Timing driven placement

Abstract: The invention is a method of designing an integrated circuit in which the steps of designing the circuit are optimized by a formal hierarchy. This method, called Timing Driven Placement, of designing an integrated circuit avoids detailed optimization which consumes enormous computational resources. It organizes physical and logical characteristics of the design so that those characteristics can be optimized with respect to the physical design of the circuit. The characteristics are optimized and the resulting circuit to location assignment is placed and wired with a conventional automated process. The method optimizes the global placement into precincts of logic segments of the circuit design with respect to the segment placement effect on circuit timing and wireability. The method then migrates individual circuits within particular segments to other segments to improve both the individual segment and overall circuit timing and wireability. Finally, the method transfers circuit assignment to logic segment and logic segment assignment to physical location information to a conventional process for final detailed circuit placement and wiring.

Computer-aided design for VLSI circuit manufacturability

Abstract: It is noted that the nominal design created by CAD tools must often be modified to maximize manufacturing yield. Such maximization must be performed during the design to achieve an acceptable level of initial manufacturing yield and during fabrication to achieve the maximum rate of yield improvement in the entire product development cycle. The manufacturing-oriented component of the CAD of VLSI circuits is discussed. The concept of design for manufacturability is explained, and a number of issues and design problems relevant to achieving a high level of IC manufacturability are examined. An overview of needed and existing CAD tools that can be used to solve previously listed problems is presented. >

Simulation model generation from a physical data base of a combinatorial circuit

Abstract: A design layout sequence for an application specific integrated circuit such as an ECL gate array includes a schematic capture step, which results in a logic netlist file, and a placement and routing step which results in a number of various files defining, for example bias drivers, I/O macros, and relationships between chip pads and I/O signals. The design layout sequence culminates in a physical data base file. To ensure a functional design, the designer's work is simulated after both schematic capture and placement and routing using a library containing simulation models for each type of macrocell used in the design. The gate-level netlist component of the simulation models are created automatically in a computer-implemented technique that identifies each root in the combinatorial circuit, assigns each a logical value, and traverses the tree that originates from each identified root. As each tree is traversed, Boolean equations identifying the logical values at each node encountered are determined in accordance with a set of relationships pertinent to the standard circuit elements and a set of logic value assignment definitions. The resulting set of Boolean equations is used to construct the gate-level netlist that is incorporated into the simulation model of the macrocell.

Timing driven placement using complete path delays

Abstract: A methodology for standard cell or gate array designs is described. A new approach is introduced whereby the placement process is divided into a global step and a detailed step. The timing drive placement (TDP) system balances wirability and timing constraints so that the final released design meets timing criteria. This is achieved by dynamically evaluating the timing of critical paths during placement. TDP is significant because convergence to a timed wirable solution early in the physical design cycle is achieved, or else it becomes apparent that logic changes are required. >

Direct access test scheme-design of block and core cells for embedded ASICs

Abstract: Intel requires the use of a direct-access test scheme in embedded-core or block-based ASIC (application-specific integrated-circuit) designs. This scheme provides for separate testing of individual block or core cells using proven test vectors. The authors discuss the design modifications for block cells with low pin counts, user application blocks, and large cores with high pin counts. The implementation and verification of the direct-access test scheme in a block- or core-based embedded ASIC design are also briefly described. >

Integrated electric design system with automatic constraint satisfaction

Abstract: An electrical design system is described which integrates many analysis and synthesis tools in an environment of top-down circuit layout. The system allows electrical design in numerous technologies, including nMOS, CMOS, bipolar, printed circuit boards and others. Technologies and analysis or synthesis tools may be added or deleted easily, and different technologies may be employed in a single design. The system includes a database manager which maintains all information regarding the design of the circuit, and which is accessed by all of the analysis and synthesis tools to enable them to examine and modify the design. The database itself is structured as a network of electrically connected and geometrically described components. Each component in the database is considered a node, and connections among components are considered as arcs. Changes are permitted only to nodes, and constraints are imposed only upon arcs. When components are changed, the effects of the changes are propagated to surrounding components by the arcs. In this manner the database manager insures that the circuit remains properly connected throughout the design process while allowing the propagation of changes up and down the hierarchy.

Operational-amplifier compilation with performance optimization

Abstract: A method for designing analog circuits in which topological design is followed by simultaneous device sizing and layout design is described. By merging circuit and layout design into a single design process, analog circuits can be optimally designed taking layout parasitics fully into account. Using the method, a CMOS operational-amplifier compiler (OAC) has been developed. Given a set of performance specifications and process parameters, OAC generates a layout with circuit performance optimized to meet specified performance constraints. A procedural layout technique is employed to generate a compact and practical layout. A nonlinear optimization method for device sizing which relies on the results of simulations based on the circuit extracted from the layout is applied. Design experiments have shown that OAC can produce satisfactory results with respect to both circuit performance and layout density. >

Method of and apparatus for designing circuit block layout in integrated circuit

Abstract: There are provided a method of and an apparatus for designing a circuit block layout in an integrated circuit wherein minimization of a total wiring length among the circuit blocks and compaction of the circuit blocks are automatically achieved upon automatically laying out the circuit blocks and determining wiring among those circuit blocks, by initially laying out the circuit blocks using a spring model of a mass point system where circuit blocks with no size are coupled through springs, configuring at least partial circuit blocks as circles to re-lay out the circuit blocks such that there is eliminated any overlapping among the circuit blocks, compacting the external shape of an assembly of the circuit blocks by matching the external shape with the frame of a die and altering the shape of each circuit block from the circle to an actual shape.

Structured logic design method using figures of merit and a flowchart methodology

Abstract: The present invention provides a structured integrated circuit design methodology. The methodology is based on describing a two-phase logic function using a high level behavioral description flow chart, properly sizing devices to be used in the circuit for speed and reducing trial and error in circuit layout implementation using novel chip planning techniques. The methodology begins with the definition of signal types based on the circuit function that creates a particular signal and the type of input signal that feeds the circuit function. A rigid set of rules is then established for use of the signal types. Next the technical specification of the two-phase logic function is defined and utilized to create a behavioral flow chart using defined symbols. An associated database of corresponding Boolean equations is then created that defines the parameters of the various elements of the flow chart. The Boolean equations are then converted to a logic diagram either by coded state assignment or by direct implementation. The resulting logic diagram is then analyzed for speed utilizing a Figures of Merit technique for establishing device sizes. The resulting circuit design may then be carried through to layout utilizing conventional computer aided design (CAD) tools.

Stochastic evolution: a fast effective heuristic for some generic layout problems

Abstract: There are two canonical optimization problems, namely, NETWORK BISECTIONING (NB) and TRAVELING SALESMAN (TS), that emerge from the physical design and layout of integrated circuits. In this paper, we use an analogy between iterative techniques for combinatorial optimization and the evolution of biological species to obtain the Stochastic Evolution (SE) heuristic for solving a wide range of combinatorial optimization problems. We show that SE can be specifically tailored to solve both NB and TS. Experimental results for the NB and TS problems show that the SE algorithm produces better quality solutions and is faster than the Simulated Annealing algorithm in all instances considered.

Constraint generation for routing analog circuits

Abstract: An approach for generating constraints on interconnect parasitics to drive the routing of analog circuits is presented. The approach involves (a) generation of a set of bounding constraints on the critical parasitics of a circuit to provide maximum flexibility to the router while meeting the performance constraints, and (b) deriving a set of matching constraints on the parasitics from matched-node-pair and matched-branch-pair information on differential circuits. A prototype constraint generator is described. It is hoped that the constraint-based approach suggested in this paper, if applied to both placement and routing, will reduce the need of time consuming layout-extraction-simulation iterations in the physical design phase of analog circuits. >

Design management based on design traces

Abstract: VOV is an automatic manager for VLSI design. It is based on the idea that CAD tools can leave a trace of their execution. The trace is represented as a bipartite directed and acyclic graph, in which the nodes represent either design data or CAD transactions. By managing and analyzing the traces, VOV offers a wide variety of services related to design management, such as coordination of team design, automatic execution of CAD transactions, and capture of design history and data dependencies. All of these services are provided in a nonintrusive fashion. VOV has the notion of measurement on the design data, an ingredient which is necessary to provide even more services: tracking of design specifications, validation of design data, and design estimation. >

Method and apparatus for power-source wiring design of semiconductor integrated circuits

Abstract: Disclosed is an apparatus for power-source wiring design of semiconductor integrated circuits including a theoretical lattice setting device for setting lattice to divide the surface of a semiconductor substrate sectional regions, an extracting device for extracting electric characteristics of each sectional region, and an operation device for obtaining circuit characteristics of each sectional region. Also disclosed is an apparatus for power-source wiring design of semiconductor integrated circuits comprising a trial circuit generating device for generating a circuit model of power-source.ground wiring of a semiconductor integrated circuit on trial, an analysis device for analyzing electric characteristics of each sectional region of the circuit model, and a comparison device for comparing the analysis result of electric characteristics obtained by the analysis device to the circuit model with an analysis result of electric characteristics previously obtained by the analysis device to a circuit model previously obtained, and estimating the former analysis result, and an improving plan generating device for generating information of a plan to improve the circuit model preferably in accordance with the comparison estimation result by the comparison device, and giving the information to the trial circuit generating device.

Automatic synthesis of integrated circuits employing controlled input dependency during a decomposition process

Abstract: A method of automatic synthesis of a very large scale integrated circuit includes controlling the decomposition process in accordance with a reference order of inputs in a lexicographical expression of a Boolean function. The process improves the routability of the circuit by a reduction of complexity of wiring between cells of the circuit and external wiring to blocks connected to the synthesized circuit. The process also promotes an increase in speed and/or a decrease in area of the circuit, avoids ineffective decompostions which would be broken later during an optimization process and also helps to speed up the entire process of synthesis.

Method and apparatus for integrated circuit design

Abstract: An integrated circuit is designed by determined the devices comprising the integrated circuit and determining the desired parameters for each device. A flow of process steps is determined and the 1-D and 2-D simulations are performed on the process flow. The process steps are modified until the simulations determine that the desired parameters are met.

Logic compiler for design of circuit models

Abstract: A logic compiler wherein verification of a generated circuit model is performed automatically by comparing the operation of the circuit model with that of a corresponding mathematical behavior model. A novel user interface and circuit model generation means enables the user to obtain, in real time, performance specifications on the circuit selected by the user as well as incurring other benefits.

Clock buffers arranged in a peripheral region of the logic circuit area

Abstract: In designing an integrated circuit having a logic circuit area and a clock supplying circuit, the layout of the clock supplying circuit can be designed before the completion of the layout designing of the logic circuit area. Clock buffers and wires that are component elements of the clock supplying circuit are arranged in a peripheral region of the logic circuit area. This arrangement enables the layout designing of the clock supplying circuit to be done with no influence of the layout designing of the logic circuit area.

Integrated circuit built-in self-test structure

Abstract: A built-in, self-test structure for the circuit components of an integrated circuit chip is isolated from the chip circuitry and the operating power supply and power supply interconnections of the chip, so that it appears as an open circuit during normal operation of the chip. The self-test structure includes separate power supply leads for connection to a separate test power supply which is employed to both enable and operate the circuit in the test mode. The test input are multiplexed on the test power supply leads while test power is applied thereto. Whenever the test power is removed, the test circuit automatically powers down and disconnects, essentially becoming invisible to the normal operation of the circuit. If short circuits or circuit opens should occur in the test structures, the reliability of the operation of the integrated circuit device itself is unaffected, since the test circuit structures are isolated from the operating circuit components of the integrated circuit chip.

Physical design of testable VLSI: techniques and experiments

Abstract: It is shown that the layout of VLSI circuits can affect testability and in some cases reduce the number of faults likely in a design, easing test generation. A method for analyzing circuits at the symbolic layout level and enhancing testability using local transformations is presented. To demonstrate the application of the technique a set of CMOS standard cells was redesigned. The standard cells are used in the MIS synthesis system, allowing the designer to modify interactively designs to perform tradeoff analysis on testable designs. To show the usefulness of the technique, an experiment was performed: example circuits were synthesized, and test vectors were generated and then used in a transistor-level fault simulator. It was found that the modified designs have significantly higher fault coverage than unmodified designs. A strategy for the synthesis of easily testable combinational random logic circuits is presented. >

CREATE-LIFE: a modular design approach for high performance ASICs

Abstract: CREATE-LIFE (Compiler for REgular ArchiTEcture, Long Instruction Format Engine) is an architecture-specific design approach for CMOS VLSI based on block modularity and architecture regularity. It takes as input a description of the function to be performed by a VLSI circuit using general-purpose. Pascal-like programming language and a description of the particular LIFE architecture instance. The output is the CMOS layout of a very high-performance (micro) programmed architecture tailored for that specific function. The LIFE architectures generated in the design environment are the single-chip implementations of an improved form of a very long instruction work (VLIW) architecture that uses both parallelism and pipelining. With this approach, an experimental general-purpose processor which performs in the 50 to 100 VAX equivalent range has been designed. >

Method for interconnection between an integrated circuit and a support circuit, and integrated circuit suitable for this method

Abstract: The invention relates to a method for interconnection of an integrated circuit on a support, replacing connecting wires. According to the invention, an integrated circuit chip (1) is fixed on a support (4) by soldering the metallisations of the earth plane (18, 20). However, the input/output lands (7, 13) of the integrated circuit are joined to the metallised tracks (8, 9) of the support (4) by means of metallised holes (14, 15). Application to UHF circuits.

Experiments using automatic physical design techniques for optimizing circuit performance

Abstract: A system is described that accepts a transistor-level net list, tunes it for high performance, and automatically lays it out. The system consists primarily of two components, TILOS and SC2D. TILOS adjusts transistor sizes and reorders series devices to meet user-supplied performance specifications, while using the smallest size transistors possible. The sized net list is placed and routed by SC2D, which produces a virtual-grid layout ready for compaction. The algorithms and procedures involved in these two tools are described, and their effect is illustrated with several examples, ranging from hundreds to tens of thousands of transistors. >

Three-dimensional routing for multilayer ceramic printed circuit boards

Abstract: An efficient three-dimensional (3-D) routing technique is presented for multilayer ceramic printed circuit (PC) boards. The router can take account of via length as well as pattern length. In the first of the two steps involved, it searches in the direction of via depth from start and end points only. This is called two-and-a-half-dimension (2.5-D) routing. Step two combines 2-D and 3-D routing for wiring not covered in step one. This enables tens of thousands of wires to be routed at 99% effectiveness in less than four hours of CPU time, with all delay conditions satisfied. >

Method of designing three dimensional electrical circuits

Abstract: A computer aided design package is used to create a mathematical representation of a three-dimensional object. This object is defined as a set of surfaces oriented in space. A map of the flattened object is created by concatenating selected ones of the surfaces on a single plane. The outline of this map is then used in a computer aided circuit layout package as a printed circuit board on which an electrical circuit is placed and routed. The circuit is translated into a three-dimensional form corresponding to the surface of the object by translating and rotating the representation of the object to align each selected surface with the circuit description generated by the circuit layout package. The portion of the circuit corresponding to the surface is then transferred to a three-dimensional data structure having a format that is compatible with numerically controlled machining apparatus. This data structure is used to drive a numerically controlled phototool which creates a three-dimensional mask that may be used to print the circuit on the surface of the three-dimensional object.

A new simultaneous circuit partitioning and chip placement approach based on simulated annealing

Abstract: The problems of circuit partitioning and chip placement have been studied in the past Given a circuit partitioned into chips, one can optimize the placement of the chips on a printed circuit board with regard to a given cost function Conversely, given a placement of the chips on the board, one can optimize the partitioning of the circuit into the chips with regard to the same cost function However, given neither the circuit partitioning nor the chip placement, we are faced with a difficult optimization problem Our target technology is one in which the chips are unpackaged chips placed on a substrate, analogous to the printed circuit board and interconnected together with high density interconnect to realize a complex system We propose a new approach in which the circuit is both partitioned and placed simultaneously by a simulated annealing based algorithm Our approach is seen to yield excellent results in reasonable run times