Showing papers on "Polysilicon depletion effect published in 1991"

Switched capacitor analog circuits using polysilicon thin film technology

Abstract: Switched capacitor analog circuits (such as integrators, amplifiers and digital-to-analog converters) constructed from polysilicon thin film transistors and capacitors are disclosed. The circuits are commonly implemented using conventional single crystal CMOS technologies, but this is the first time they have been realized using polysilicon TFT CMOS. The performance of the circuits is inevitably worse than that of conventional single crystal CMOS devices, but is nevertheless adequate for many large area applications. The circuits can be fabricated on large area substrates and integrated with, for example, flat panel displays, pagewidth optical scan arrays, or pagewidth printheads, offering improvements in the functionality and performance of those devices. Charge redistribution amplifiers and digital-to-analog converters are shown to operate with settling times ranging from a few microseconds to a few tens of microseconds, even with large capacitive loads, despite the relatively poor performance of polysilicon TFTs in comparison to conventional MOSFETS. Better than 8-bit accuracy is also demonstrated for the digital-to-analog converters.

Avalanche-induced effects in polysilicon thin-film transistors

Abstract: A comparison of experimental data and two-dimensional numerical simulations of polysilicon thin-film transistors (TFTs) is presented. It is shown that avalanche multiplication causes both the kink effect in the output characteristics and the reduction of threshold voltage in short-channel device. It is shown that exactly the same physical model for avalanche multiplication gives very good agreement between simulations and experimental data for both these effects. It is demonstrated that it is the presence of grain boundaries or traps in the polysilicon that causes avalanche effects to be much greater than in comparable single-crystal silicon devices. >

A floating-gate MOSFET with tunneling injector fabricated using a standard double-polysilicon CMOS process

Abstract: A floating-gate MOSFET which is programmable in both directions by Fowler-Nordheim tunneling and is fabricated using an inexpensive standard 2- mu m double-polysilicon CMOS technology is discussed. Tunneling occurs at a crossover of polysilicon 1 with polysilicon 2. Device layout and basic device characteristics are presented, and recommendations for efficient programming are given. This is the first floating-gate FET with a tunneling injector fabricated in standard technology that has close to symmetric programming characteristics for both charging and discharging of the gate. >

Investigation of boron diffusion in polysilicon and its application to the design of p-n-p polysilicon emitter bipolar transistors with shallow emitter junctions

Abstract: Ion implantation of boron into undoped polysilicon is utilized. The main goals are to characterize the diffusion of implanted boron from polysilicon, and to correlate the diffusion behavior with the electrical properties of shallow ( >

PROM and ROM memory cells

Abstract: An antifuse memory cell having a P + polysilicon doping in a region directly under an intrinsic silicon programming layer. The P + polysilicon region is surrounded by an N - polysilicon doped region, and the two regions are sandwiched between layers of silicon dioxide insulation. The interface between the two regions is a P-N junction, in fact, a diode. The diode does not suffer from a diffusion current that increases with increasing levels of N - doping, therefore the N - polysilicon can be heavily doped to yield a very conductive bit line interconnect for a memory matrix. The interconnect line widths can be very narrow, and further microminiaturization is aided thereby. The top metalization is aluminum and serves as a word line interconnect in the memory matrix.

A method for the fabrication of low leakage polysilicon thin film transistors

Abstract: A method of manufacturing a thin film transistor having a low leakage current including depositing a layer of silicon oxide on a semiconductor substrate or on a layer of silicon nitrate deposited on a glass substrate, depositing a polysilicon layer, at a temperature of 520°-570° C., on the silicon oxide layer, annealing this polysilicon layer in a nitrogen atmosphere at a temperature of less than 650° C., forming islands in this polysilicon layer, forming a gate oxide layer on one of the islands by oxidizing the island under high pressure at a temperature below 650° C., forming a gate from a heavily doped polysilicon layer deposited on the gate oxide layer, forming lightly doped source and drain areas laterally adjacent to the gate, providing a thin layer of silicon oxide on the gate and the source and drain access, heavily doping areas of the first silicon layer adjacent to the source and drain areas, annealing the source and drain areas at a temperature below 650° C. and hydrogenating the resistive transistor with a hydrogen plasma.

Gate oxide damage from polysilicon etching

Abstract: Damage to thin gate oxides from etching of polysilicon gates was studied using gate oxide breakdown histograms and time‐dependent dielectric breakdown measurements. The effect of various polysilicon etch parameters was investigated in a radio frequency (rf) triode etcher. Increasing rf power caused a substantial increase in damage. Reducing bias at constant power also resulted in an increase in damage, indicating that ion energy is not the only cause of damage. Area, isolation edge, and source/drain edge contributions to gate oxide defect densities were calculated as a function of rf power during polysilicon etch. As rf power was increased, the area contribution increased the most, indicating that gate oxide damage from polysilicon etching is not an edge phenomenon but a surface phenomenon. The effect of gate oxide thickness was investigated. Damage increased significantly as gate oxide thickness was reduced. Finally, the rf triode etcher was compared with a microwave electron cyclotron resonance (ECR) et...

Textured polysilicon stacked trench capacitor

Abstract: A trench capacitor structure suitable for inclusion in integrated circuit devices and method for forming the same provides increased electrode surface area and capacitance by means of a textured surface of one of the capacitor electrodes. The textured surface is achieved by differentially etching grain boundaries of a doped polysilicon layer or by direct deposition of hemispherical grain polysilicon to form the electrode. Additional capacitance and contact area can be obtained by additional etching of the trench bottom prior to electrode deposition and dielectric growth.

Method of forming a capacitor in semiconductor wafer processing

Abstract: A method of forming a capacitor in semiconductor water processing comprising the following steps: a) providing a conductively doped first layer of polysilicon atop a silicon wafer to a first thickness; b) depositing an undoped second layer of polysilicon over the conductively doped first layer of polysilicon to a second thickness, the layer of undoped polysilicon being deposited at a deposition temperature of at least 590° and having an upper surface; c) impinging laser energy onto the upper surface of the second polysilicon layer at a laser fluence of 0.3 J/cm 2 or greater to roughen the upper surface and thereby increase the capacitance of the second polysilicon layer; d) patterning and etching the first and second polysilicon layers to define a lower capacitor plate; e) providing a layer of capacitor dielectric atop the roughened second polysilicon layer upper surface; and f) providing a layer of conductive material atop the capacitor dielectric to define an upper capacitor plate.

Erase performance improvement via dual floating gate processing

Abstract: A process for fabricating floating gates for electrically programmable and electrically erasable memory cells of the flash EPROM or EEPROM type. The floating gates are a three layer structure. The first layer of the floating gate is a thin polysilicon layer of approximately 300-500 Å thickness. The second layer is a silicon dioxide layer of approximately 20-30 Å. The third layer is polysilicon of approximately 1000-1500 Å thickness. The third layer is doped by implantation of phosphorous. This dopant is driven through the oxide layer to dope the first, thin polysilicon layer in a separate diffusion step or in subsequent high temperature processing. The grain size of the first, thin polysilicon layer is small and uniform from gate to gate due to the thinness of this layer and its light doping. This reduces variations in threshold voltage from gate to gate due to variable polysilicon grain size and orientation. This in turn results in improved yield and cycling endurance.

Silicide formation on polysilicon

Abstract: An integrated circuit includes a doped polysilicon/silicide ("polycide") gate electrode. The doped polysilicon layer comprises sub-layers. The sub-layers are formed by varying the silicon deposition conditions, typically including the deposition rate, while decreasing the dopant concentration. The metal silicide layer is then formed on top of the doped polysilicon layer. An improvement in uniformity and planarity of the structure is obtained as a result of stress accommodation. In addition, the sub-layers reduce the channeling effect that occurs during high energy source/drain dopant implantation. These effects allow for a reduced stack height of the gate electrode, resulting in improvements in very small (sub-micron) device structures.

Self-aligned cylindrical stacked capacitor DRAM cell

Abstract: A method for fabricating a dynamic random access memory having a high capacitance stacked capacitor begins by selectively forming relatively thick field oxide areas on the surface of a semiconductor substrate while leaving device areas for fabrication of field effect devices. A gate dielectric layer is formed on the substrate in the device areas. A relatively thick first layer of polysilicon is deposited on the field oxide areas and the device areas. Portions of the first polysilicon layer is removed while leaving portions thereof for the gate structure in the device areas, and portions over the field oxide areas. A first insulator layer composed at least in part of silicon nitride is formed over the device and field oxide areas. The stacked capacitors are now formed by first depositing a second polysilicon layer over the device and field oxide areas. An etch mask is now formed on the second polysilicon layer and the second polysilicon layer is anisotropically etching to form a shell-shaped second polysilicaon layer. A capacitor dielectric layer is formed over the shell-shaped second polysilicon layer. A third polysilicon layer is deposited and patterned as the top storage node electrode to complete the stacked capacitors. The etch mask can either be formed in part by a lateral etching of a resist mask or is formed in part by use of a sidewall spacer structure and mask. The first insulator layer is patterned to expose the source/drain structures to electrical contact either before or after the deposition of the second polysilicon layer.

Method for maintaining the resistance of a high resistive polysilicon layer for a semiconductor device

Abstract: A method for depositing a passivation layer on a semiconductor structure having a high resistance value polysilicon layer formed thereon while maintaining the high resistance value thereof and comprises sequentially depositing a silicon oxide layer and a silicon nitride layer, on a high resistance value polysilicon layer of a partially completed semiconductor structure to form a passivation layer thereover. The passivation layer including the silicon oxide layer and the silicon nitride layer is annealed with oxygen plasma in a chamber. The annealed passivation layer is then heated in the presence of a conditioning gas in the chamber to thereby maintaining the resistance of the high resistance value polysilicon layer.

High-Mobility Bottom-Gate Thin-Film Transistors with Laser-Crystallized and Hydrogen-Radical-Annealed Polysilicon Films

Abstract: High-performance bottom-gate thin-film transistors (TFTs) have been realized with excimer-laser-crystallized polysilicon films, for the first time. TFT characteristics were greatly dependent on the silicon film thickness as well as the pulsed-laser energy density. It was found also that posthydrogenation based on hydrogen-radical annealing improves the TFT characteristics drastically. The field-effect mobilities exceeded 220 cm2/Vs for electrons and 140 cm2/Vs for holes, respectively.

Semiconductor device having variable impurity concentration polysilicon layer

Abstract: The present invention relates to a semiconductor device used as a gate electrode or interconnection, in which a polysilicon layer in a laminate comprising a polysilicon layer doped with an impurity and a refractory metal silicide layer has an impurity concentration that is reduced close to a boundary between the polysilicon layer and the refractory metal silicide layer. With this structure, the difference in oxidation speed between the polysilicon layer and the silicide layer is smaller in comparison with a conventional structure, and thus peeling due to bird's beaks can be prevented. The semiconductor device of this structure can be realized by a two-layer polysilicon structure in which the upper layer in contact with the refractory metal silicide layer has a lower impurity concentration, or by a structure in which the peak of the impurity concentration profile is set to be deep within the polysilicon layer during ion implantation.

Stacked capacitor dram cell and method of fabricating

Abstract: A DRAM having stacked high capacitance capacitors formed by depositing a thick undoped polysilicon layer over field oxide areas thereon, patterning the polysilicon layer so as to have portions over the planned stacked capacitor areas, forming a silicon oxide layer on the exposed surface of the polysilicon, removing the silicon oxide layer from horizontal surfaces of the polysilicon layer by anisotropic etching, removing the polysilicon layer by isotropic etching leaving vertical silicon oxide structures, and forming openings to desired source/drain structures of the DRAM using lithography and etching. A bottom electrode polysilicon layer is deposited over the device and field oxide areas to make contact to the source/drain structures. A capacitor dielectric layer is formed over the bottom electrode polysilicon layer. A contact polysilicon layer is deposited as the top storage node electrode and the contact polysilicon layer and the dielectric layers are patterned.

Process for fabricating polysilicon resistors and interconnects

Abstract: A process for faricating polysilicon resistors and polysilicon interconnects coupled to MOS field-effect devices in a silicon substrate includes the steps of depositing and etching a first polysilicon layer to form the gates of the MOS devices; then depositing a second layer of polysilicon between the gates. The second polysilicon layer is then etched so that its upper surface is substantially coplanar with the gates. Contact openings are then defined to the source, drain and gate members of the devices through an insulative layer formed over the first and second polysilicon layers. Next, a metal layer is deposited to fill the openings and is patterned to define electrical contacts to the devices. The patterning step also defines the interconnect lines in the metal layer. A third polysilicon layer is then deposited and patterned to define the polysilicon resistors and interconnects.

Bicmos device and manufacturing method thereof

Abstract: A BICMOS device and manufacturing method wherein the gates of PMOS and NMOS transistors are formed by forming a first polysilicon layer which is not implanted by an impurity and forming a second polysilicon layer on the first polysilicon layer which is impurity implanted, so that the impurity doped in the second polysilicon layer is prevented from diffusing into the channel region and the voltage characteristic is prevented from changing. Emitter regions of vertical PNP and NPN bipolar transistors are self-aligned in a small chip area, and thereby the performance of the BICMOS device is improved due to the stable threshold voltage characteristic of the PMOS and NMOS transistors and high density is achieved together with improved operation speed clue to the self-alignment formation of the emitter region of the vertical PNP and NPN bipolar transistors.

Double polysilicon capacitor formation compatable with submicron processing

Abstract: A method for fabricating an integrated circuit having a double polysilicon capacitors and metal oxide silicon field effect devices which are compatible to one micrometer or less processing is described. First, a pattern of recessed oxide isolation is formed on the surface of a silicon substrate. The pattern separates surface regions of silicon from other such regions. A gate dielectric layer is formed on the surface of surface regions of the silicon with a suitable dopant concentration. A first polysilicon layer is formed over the gate dielectric layer and over the field oxide having a suitable doping concentration. An interpoly dielectric layer is formed over the surface of the first polysilicon layer. A second poly silicon layer is formed over the interpoly dielectric layer having a suitable doping concentration. The second polysilicon layer is patterned using a first resist masking and suitable etching to leave only the top plate of the capacitor in the second polysilicon layer. The interpoly dielectric layer is removed except where it is located beneath the top plate by using top plate of the capacitor in second polysilicon layer as the etching mask. The first polysilicon layer is now patterned using a second resist masking and suitable etching to leave only the bottom plate of the capacitor and the gate electrode of the transistor in the first polysilicon layer. The second resist masking layer is removed. The elements of the integrated circuit are completed by conventional processing.

Method of producing insulated-gate field effect transistor

Abstract: A polysilicon layer of approximately 500Å in thickness and a PSG layer approximately 3000Å in thickness are sequentially layered on a silicon wafer on which a gate insulating layer is formed; an opening having been formed in the PSG layer. After forming a side wall layer made of PSG of predetermined thickness in the opening, a second polysilicon layer for a leg portion of an inverse-T gate is embedded in the opening and both PSG layers are removed. Then, n - impurities are doped by ion implantation by using the second polysilicon layer as a mask, forming a LDD region. Another side wall layer is formed on the second polysilicon layer, and then, the first polysilicon layer, exposed outside of the second polysilicon layer and the side wall layer, is etched. Under the side wall layer, that polysilicon layer constituting a top of the inverse-T gate remains. Ion implantation is implemented by using the second polysilicon layer and the side wall layer as masks, such that a n + source and n + drain are formed. Since the n - impurities are doped by the ion implantation through the first polysilicon layer having an even thickness, the junction depth in the LDD region is constant. Additionally, since the thickness of the first polysilicon layer is small, the gate insulating layer reliably functions as an etch-stop in patterning the polysilicon layer.

Method of forming an inverse T-gate FET transistor

Abstract: A method of forming an LDD field effect transistor with an inverted "T"-gate structure in which consecutive, conformal layers of polysilicon, metal and nitride or oxide are deposited to fill the recess in a composite interconnect layer on top of a trench isolated region of a semiconductor substrate. These conformal layers successively decrease in thickness and are selectively etched in two steps to form a self-aligned inverted T structure. A first reactive ion etch (RIE) step preferentially etches the exposed outer polysilicon to a certain depth. During a second step RIE the polysilicon layer is completely etched down to the a gate oxide surface and the metal layer is preferentially etched so that subtends only the remaining nitride or oxide cap.

Method of making extended polysilicon self-aligned gate overlapped lightly doped drain structure for submicron transistor

Abstract: For a structure with an overlapping gate region, a first insulator layer is placed on a substrate. A source/drain polysilicon layer is placed on the insulator layer. The source/drain polysilicon layer is doped with atoms of a first conductivity type. A second insulator layer is placed on the source/drain polysilicon layer. A gap is etched in the second insulator layer and the source/drain polysilicon layer to expose a portion of the first insulator layer. The exposed portion of the first insulator layer and an additional amount of the first insulator layer under the second insulator is etched so as to enlarge the gap and to undercut a portion of the source/drain polysilicon layer. Two polysilicon filler regions are formed which fill a portion of the gap including the undercut area under the source/drain polysilicon layer. A gate polysilicon region is formed in the gap and extends over the source/drain polysilicon layer. The gate polysilicon region is separated from the source/drain polysilicon layer and the polysilicon filler regions by a dielectric region. Source/drain regions are formed by atoms in the source/drain polysilicon layer diffusing through the polysilicon filler regions into the substrate.

Semiconductor device and method of production

Abstract: A novel semiconductor device and method of production of such a device are provided. Both the N and P channels of the novel semiconductor device are formed by contact self-alignment, thereby permitting high speed operation and high density integration to be realized. The formation of the channels by contact self-alignment is accomplished by depositing a P type polysilicon layer on an N well region and an N type polysilicon layer on a P well region. A silicide layer is formed over both the P and N type polysilicon layers to form a polycide.

MOSFET fabrication process with lightly-doped drain using local oxidation step to pattern gate electrode

Abstract: A gate oxide layer, a polysilicon layer, and an oxidation-resistant layer are formed in sequence on a semiconductor substrate, the oxidation-resistant layer is patterned, then high-pressure oxidation is performed, oxidizing at least part of the polysilicon layer not covered by the oxidation-resistant layer and leaving, under the oxidation-resistant layer, a polysilicon gate electrode with tapered sides. The oxidized portions of the polysilicon layer are removed and two ion implantation steps are carried out with different accelerating energies and impurity doses, one step creating heavily-doped source and drain areas, the other step creating lightly-doped offset layers. The lightly-doped offset layers are at least partially located under the tapered sides of the gate electrode.

Polysilicon encapsulated local oxidation

Abstract: Polysilicon encapsulated local oxidation (PELOX) is proposed as an effective isolation technique that satisfied advanced device requirements without any difficult-to-control structures or processes. Simple modifications to a standard local oxidation of silicon (LOCOS) process flow minimize encroachment without introducing defects. These modifications include an HF dip after nitride patterning to form a cavity self-aligned to the nitride edge, reoxidation of exposed silicon, and polysilicon deposition to fill the cavity. Physical (scanning electron micrographs) and electrical (gate oxide quality, diode integrity, and W/sub eff/) data which indicate that cavity reoxidation is critical to obtaining significant bird's beak reduction without defect introduction are presented. >

Method of fabricating semiconductor memory device having a cylindrical capacitor electrode

Abstract: A method of fabricating capacitor electrodes in a stacked type of a dynamic random access memory (DRAM) is disclosed. This method of fabricating the capacitor electrodes of a storage capacitor in the semiconductor memory device having a memory cell comprising a MOS transistor and a storage capacitor includes the steps of forming a highly doped polysilicon film, patterning the highly doped polysilicon film in a predetermined shape, forming a lightly doped polysilicon film so as to cover the surface of the highly doped polysilicon film, and anisotropically etching the lightly doped polysilicon film. A cylindrical capacitor electrode having a bottom portion in a stacked type of memory cell can be easily formed. By increasing the height of the cylindrical portion, the area of the electrodes opposing with each other of the storage capacitor can be also easily increased.

Process for depositing highly doped polysilicon layer on stepped surface of semiconductor wafer resulting in enhanced step coverage

Abstract: A polysilicon deposition process is disclosed for forming a doped polysilicon layer over a stepped surface on a semiconductor wafer having the deposition characteristics and resulting profile of an undoped polysilicon layer which comprises: depositing doped polysilicon on the stepped surface, depositing undoped polysilicon over the doped polysilicon, repeating the doped and undoped depositions cyclically until the desired amount of polysilicon has been deposited, and then annealing the deposited polysilicon to uniformly distribute the dopant throughout the entire deposited polysilicon layer.

Method for manufacturing a multi-layer gate electrode for a mos transistor

Abstract: A multi-layer gate electrode is provided to prevent dopant depletion of a polysilicon in the manufacture of the electrode containing doped polysilicon and metal silicide. First, a multi-layer structure is produced containing a doped polysilicon structure, a diffusion barrier structure and a silicon structure. After deposition of a metal layer covering the multi-layer structure, a metal silicide structure is produced from the silicon structure and the metal layer in a tempering process. The diffusion barrier structure thereby prevents diffusion of dopant out of the polysilicon structure into the metal silicide structure. This may be used in a salicide process.

Unified minority-carrier transport equation for polysilicon or heteromaterial emitter contact bipolar transistors

Abstract: An analytical minority-carrier transport equation is derived that unifies the various models for polysilicon-emitter contact bipolar transistors. The theory covers drift and diffusion in the arbitrary doped crystal-silicon-emitter region, recombination and tunneling at the polysilicon-silicon interface and the potential barrier associated with heteromaterial, and diffusion in the polysilicon emitter region. The ratio of recombination current at the interface and diffusion current in the polysilicon to the total hole current is formulated using this theory. The influence of the two-dimensional structure of the oxide at the polysilicon-silicon interface on current gain is also analyzed. The theory is applied to the heterojunction bipolar transistor (HBT), and it is found that the recombination velocity at the heteromaterial-silicon interface should be suppressed to less than 10/sup 4/ cm/s. >