Showing papers on "Polysilicon depletion effect published in 2015"

Method for producing semiconductor device and semiconductor device

Abstract: A SGT production method includes a step of forming first and second fin-shaped silicon layers, forming a first insulating film, and forming first and second pillar-shaped silicon layers; a step of forming diffusion layers by implanting an impurity into upper portions of the first and second pillar-shaped silicon layers, upper portions of the first and second fin-shaped silicon layers, and lower portions of the first and second pillar-shaped silicon layers; a step of forming a gate insulating film and first and second polysilicon gate electrodes; a step of forming a silicide in upper portions of the diffusion layers formed in the upper portions of the first and second fin-shaped silicon layers; and a step of depositing an interlayer insulating film, exposing and etching the first and second polysilicon gate electrodes, then depositing a metal, and forming first and second metal gate electrodes.

Ultrahigh selective polysilicon etch with high throughput

Abstract: Provided are methods and apparatuses for removing a polysilicon layer on a wafer, where the wafer can include a nitride layer, a low-k dielectric layer, an oxide layer, and other films. A plasma of a hydrogen-based species and a fluorine-based species is generated in a remote plasma source, and the wafer is exposed to the plasma at a relatively low temperature to limit the formation of solid byproduct. In some implementations, the wafer is maintained at a temperature below about 60° C. The polysilicon layer is removed at a very high etch rate, and the selectivity of polysilicon over the nitride layer and the oxide layer is very high. In some implementations, the wafer is supported on a wafer support having a plurality of thermal zones configured to define a plurality of different temperatures across the wafer.

Sub-bandgap polysilicon photodetector in zero-change CMOS process for telecommunication wavelength.

Abstract: We report a defect state based guided-wave photoconductive detector at 1360–1630 nm telecommunication wavelength directly in standard microelectronics CMOS processes, with zero in-foundry process modification. The defect states in the polysilicon used to define a transistor gate assists light absorption. The body crystalline silicon helps form an inverse ridge waveguide to confine optical mode. The measured responsivity and dark current at 25 V forward bias are 0.34 A/W and 1.4 μA, respectively. The 3 dB bandwidth of the device is 1 GHz.

Select gate transistor with single crystal silicon for three-dimensional memory

Abstract: A fabrication process for a 3D memory structure provides a single crystal silicon channel for a drain-side select gate (SGD) transistor using a laser thermal anneal (LTA). The 3D memory structure includes a stack formed from an array of alternating conductive and dielectric layers. A NAND string is formed by filling a memory hole with memory films, including a charge trapping material, a tunnel oxide and a polysilicon channel. In one case, a separate oxide and polysilicon forms the SGD transistor gate oxide and channel respectively, where LTA is performed on the polysilicon. In another case, the same oxide and polysilicon are used for the SGD transistor and the memory cells. A portion of the polysilicon is converted to single crystal silicon. A back side of the single crystal silicon is subject to epitaxial growth and thermal oxidation via a void in a control gate layer.

High-Contrast Polysilicon Grating Reflectors Implemented in a Standard Bulk CMOS Line

Abstract: A high-index-contrast grating (HCG) reflector is implemented in the polysilicon gate of a standard bulk CMOS for the first time. A transverse-electric (TE) preferred CMOS HCG reflector allows a >90% peak reflectivity, a 100-nm reflection bandwidth, and a 1.64:1 TE/transverse-magnetic polarization ratio, which is limited by the thin field oxide layer between the HCG and the silicon substrate, resulting in optical leakage to the substrate. Remarkable improvements in peak reflectivity (close to 100%) and polarization ratio (10:1) are achieved by removing the substrate of HCG devices. Guided-mode resonance reflection in HCGs is further verified by the corresponding transmission dips and is predicted by the rigorous coupled-wave analysis simulations.

Manufacture method of polysilicon thin film and polysilicon tft structure

Abstract: The present invention provides a manufacture method of a polysilicon thin film and a polysilicon TFT structure. The manufacture method of the polysilicon thin film comprises: step 1 , providing a substrate ( 1 ), and forming the polysilicon thin film ( 3 ) on the substrate ( 1 ), and a thickness of the polysilicon thin film ( 3 ) accords with a required thickness of manufacturing a semiconductor element; step 2 , implementing silicon self-ion implantation to the polysilicon thin film ( 3 ), and an implantation volume of silicon ion is lower than a measurement limit for making polysilicon be decrystallized. The manufacture method of the polysilicon thin film makes the implanted silicon ion to form interstitial silicon to move to the polysilicon grain boundary, which can reduce the defect concentration of the polysilicon grain boundary and improve the quality of the polysilicon thin film. The present invention provides a polysilicon TFT structure, of which the island shaped semiconductor layer is manufactured by the polysilicon thin film after low volume silicon self-ion implantation, which can reduce the grain boundary potential barrier in the activation stage, and enlarge the carrier mobility, and increase the on state current, and decrease the threshold voltage, and improve the TFT property.

NMOS drive current enhancement by reducing mechanical stress induced by Shallow Trench Isolation

Abstract: This paper presents a new solution to reduce the mechanical stress impact of Shallow Trench Isolation (STI) by adding polysilicon in STI and thus, improve MOSFET performances. Indeed, when a polysilicon wall is used, the drive current of NMOS transistors used in analog and digital applications is 5% higher due to the reduction in the STI-induced, compressive stress in the channel. The polysilicon wall could be added automatically in digital standard cells during cad to mask operation without increasing the size of the cells. Finally, the speed frequency of CMOS inverter ring oscillators designed with low-voltage MOSFETs used in digital standard cells is increased by 6% when a polysilicon wall is added around NMOS transistors. Moreover, the static current of ring oscillators remains unchanged.

Method for integrating non-volatile memory cells with static random access memory cells and logic transistors

Abstract: A method of making a semiconductor device is described. The method comprises depositing a first polysilicon layer in a non-volatile memory (NVM) region and a logic region of a substrate. A first coating layer is deposited over the first polysilicon layer. The first coating layer and the first polysilicon layer are patterned to form a first gate in the NVM region. A memory cell is formed including the first gate. The first coating layer and the first layer of polysilicon in the logic region are removed and a logic gate polysilicon layer is deposited. The logic gate polysilicon layer is patterned to form a second gate in the logic region while the logic gate polysilicon layer is removed from the NVM region. Source/drain regions of the memory cell and the second gate are implanted concurrently.

Design optimization of high-k dielectric based double-gate MOSFET and it's performance

Abstract: In Micro and Nano Technology, the downscaling of semiconductor devices requires the usage of alternative semiconductor material for SiO2 as the gate dielectric. It requires new structure so that the higher current can be achieved. In view of this, in the present paper a structure of double-gate MOSFET with HfO2 has been analysed. This paper includes an effect of threshold voltage on symmetric double-gate MOSFET for the application of wireless sensors networks and radio-frequency switches. By changing the structure from single-gate MOSFET to double-gate MOSFET, the threshold voltage can be change and so the leakage current and short channel effects can be decreased. Hence the switching speed of RF switch can be controlled.

Polysilicon resistor degradation - modeling and mechanism

Abstract: The resistance degradation of lightly doped Polysilicon Resistors (PR's) has been studied in detail, and the degradation rate statistically modelled. After accounting for Joule Heating [1], the resistance degradation is still observed to depend on current, indicating that current affects the degradation independent of Joule Heating.

Enhancement of Electrical Properties of Nanostructured Polysilicon Layers Through Hydrogen Passivation.

Abstract: The light absorption of polysilicon planar junctions can be improved using nanostructured top surfaces due to their enhanced light harvesting properties. Nevertheless, associated with the higher surface, the roughness caused by plasma etching and defects located at the grain boundary in polysilicon, the concentration of the recombination centers increases, leading to electrical performance deterioration. In this work, we demonstrate that wet oxidation combined with hydrogen passivation using SiN(x):H are the key technological processes to significantly decrease the surface recombination and improve the electrical properties of nanostructured n(+)-i-p junctions. Nanostructured surface is fabricated by nanosphere lithography in a low-cost and controllable approach. Furthermore, it has been demonstrated that the successive annealing of silicon nitride films has significant effect on the passivation quality, resulting in some improvements on the efficiency of the Si nanostructure-based solar cell device.

Enhancement of carrier collection efficiency in photodiodes by introducing a salicided polysilicon contact

Abstract: Suppressing recombination on silicon contact interfaces is a topic being addressed for various applications such as photo sensors and solar cells. Although salicidation of the contacts enables low contact resistance, it is usually avoided for these applications as it increases the recombination rate on the contact interfaces. This study explores the use of salicided polysilicon buffer layer in photodiodes' contacts, acting to reduce the recombination rate at the silicide contact. The contact incorporates the advantage of low contact resistance due to silicidation with polysilicon interface that reduces recombination by creating carrier selective junction. The introduction of a polysilicon interlayer was found to increase the short circuit current and the fill factor and to decrease the dark leakage current. The improvement in the light collection parameters was found to be more pronounced under high light intensity (1000 W/m2) than under low light intensity (400 W/m2). The benevolent effect of the polysil...

Semiconductor device with surrounding gate transistor

Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped silicon layer on a silicon substrate using a first resist and forming a first insulating film therearound; and a second step of forming a second insulating film around the fin-shaped silicon layer and etching the second insulating film so as to be left on a side wall of the fin-shaped silicon layer, depositing a third insulating film on the first and second insulating films and the fin-shaped silicon layer, depositing a polysilicon thereon, planarizing a surface thereof, and etching back the polysilicon to expose the third insulating film, forming a second resist, etching the second and third insulating films and then etching the fin-shaped silicon layer and the polysilicon, and removing the second insulating film to form a pillar-shaped silicon layer and a dummy gate formed of the polysilicon.

Well resistors and polysilicon resistors

Abstract: An integrated circuit containing a well resistor has STI field oxide and resistor dummy active areas in the well resistor. STI trenches are etched and filled with trench fill dielectric material. The trench fill dielectric material is removed from over the active areas by a CMP process, leaving STI field oxide in the STI trenches. Subsequently, dopants are implanted into a substrate in the well resistor area to form the well resistor. An integrated circuit containing a polysilicon resistor has STI field oxide and resistor dummy active areas in an area for the polysilicon resistor. A layer of polysilicon is formed and planarized by a CMP process. A polysilicon etch mask is formed over the CMP-planarized polysilicon layer to define the polysilicon resistor. A polysilicon etch process removes polysilicon in areas exposed by the polysilicon etch mask, leaving the polysilicon resistor.

Floating gate separation in NAND flash memory

Abstract: A method of forming a NAND flash memory includes anisotropically etching trenches of a gate stack down to an intermediate level in a floating gate polysilicon layer, leaving remaining portions of the floating gate polysilicon over the gate dielectric layer. Subsequently, forming a protective layer along exposed sides of the trenches. Then, electrically separating individual floating gates by a selective process that is directed to the remaining portions of the floating gate polysilicon layer exposed by trenches.

Poly resistor for metal gate integrated circuits

Abstract: An integrated circuit containing a metal gate transistor and a thin polysilicon resistor may be formed by forming a first layer of polysilicon and removed it in an area for the thin polysilicon resistor. A second layer of polysilicon is formed over the first layer of polysilicon and in the area for the thin polysilicon resistor. The thin polysilicon resistor is formed in the second layer of polysilicon and the sacrificial gate is formed in the first layer of polysilicon and the second layer of polysilicon. A PMD layer is formed over the second layer of polysilicon and a top portion of the PMD layer is removed so as to expose the sacrificial gate but not expose the second layer of polysilicon in the thin polysilicon resistor. The sacrificial gate is removed and a metal replacement gate is formed.

Fabrication and Characterization of Doped Polysilicon Nanowire for pH Sensor

Abstract: This paper presents the characteristics of the doped polysilicon nanowire for pH sensors. The fabrication involved two chromium mask designs. Example the first mask is used for the polysilicon nanowire pattern and the other one is for pad patterning. It involved of photolithography, deposition, etching and wet oxidation process. Different length, number of polysilicon are fabricated and then subjected to voltage, current and pH measurement. APTES is being introduced to improve the sensitivity of the polysilicon nanowire. For the low pH, the conductivity is high, while for the high pH, the conductivity is low. The impact on investigating length is insignificant to the sensitivity of the doped polysilicon nanowire.

Thin film transistor, display apparatus comprising the same, method of manufacturing thin film transistor, and method of manufacturing display apparatus

Abstract: A thin film transistor includes a polysilicon layer on a substrate, which includes a first area between second and third areas. A polysilicon layer is formed on the substrate, and a source electrode and a drain electrode are formed on the polysilicon layer in the first and third areas. Each of the source electrode and the drain electrode includes a metal silicide layer adjacent the polysilicon layer.

Method for cmp of high-k metal gate structures

Abstract: A method for manufacturing a semiconductor device includes providing a substrate containing a front-end device and forming a dielectric layer on the substrate. The front-end device includes a first dummy gate in a first type metal gate transistor region, a second dummy gate in a second type metal gate transistor region, and a polysilicon gate in a polysilicon gate region. The method also includes removing a thickness of the first, second, and polysilicon gates and forming a protective layer on the polysilicon layer to protect the polysilicon layer during a CMP process, thereby improving the performance and yield of the semiconductor device.

Retrograde-Mask Processed Polysilicon TFT for High Performance, Planar Structure, and Stable Operation

Abstract: We fabricated polysilicon thin-film transistors (TFTs) using a retrograde-mask process (RMP) showing high electrical performance, planar geometry, and stable driving characteristics. The electrical performance of RMP polysilicon TFT was compared with conventional metal-induced laterally crystallized (MILC) polysilicon TFTs. The fabrication process changed the masking steps of the conventional pattern, but did not require an additional mask. It was found that the conventional MILC poly-Si TFT typically showed a hump current, and had a serious reliability problem due to the NiSi2 contamination at the corner edges and geometry effect. One the other hand, an RMP poly-Si TFT improved the hump and the TFT’s reliability due to the absent of NiSi2 at the edges and the large effective channel length and width.

Method for forming polysilicon

Abstract: A method for forming polysilicon on a semiconductor substrate that include providing amorphous silicon on a semiconductor substrate, exposing at least an area of the amorphous silicon to a first laser beam and a second laser beam, characterized in that during exposing the area to the second laser beam no displacement of the laser beam relative to the area occurs. In addition, the use of such method for producing large grain polysilicon. In particular, the use of such method for producing vertical grain polysilicon. Further, the use of such method for producing sensors, MEMS, NEMS, Non Volatile Memory, Volatile memory, NAND Flash, DRAM, Poly Si contacts and interconnects.

Mapping stresses in high aspect ratio polysilicon electrical through-wafer interconnects

Abstract: Electrical through-wafer interconnect technologies such as vertical through-silicon vias (TSVs) are essential in order to maximize performance, optimize usage of wafer real estate, and enable three-dimensional packaging in leading edge electronic and microelectromechanical systems (MEMS) products. Although copper TSVs have the advantage of low resistance, highly doped polysilicon TSVs offer designers a much larger range of processing options due to the compatibility of polysilicon with high temperatures and also with the full range of traditional CMOS processes. Large stresses are associated with both Cu and polysilicon TSVs, and their accu- rate measurement is critical for determining the keep-out zone (KOZ) of transistors and for optimizing down- stream processes to maintain high yield. This report presents the fabrication and stress characterization of 400-μm deep, 20-Ω resistance, high aspect ratio (25:1) polysilicon TSVs fabricated by deep reactive ion etching (DRIE) followed by low-pressure chemical vapor deposition (LPCVD) of polysilicon with in-situ boron doping. Micro-Raman imaging of the wafer surface showed a maximum stress of 1.2 GPa occurring at the TSV edge and a KOZ of ∼9 to 11 μm. For polysilicon TSVs, the stress distribution in the TSVs far from the wafer surface(s) was not previously well-understood due to measurement limitations. Raman spectroscopy was able to overcome this limitation; a TSV cross section was examined and stresses as a function of both depth and width of the TSVs were collected and are analyzed herein. An 1100°C postanneal was found to reduce average stresses by 40%. © 2015 Society of Photo-Optical Instrumentation Engineers (SPIE) (DOI: 10.1117/1.JMM.14.2.024001)

Manufacturing method of low temperature polysilicon thin film transistor

Abstract: The invention provides a manufacturing method of a low temperature polysilicon thin film transistor, including: providing a substrate; forming a buffer layer on the substrate; simultaneously forming a polysilicon layer and a photoresist layer on the buffer layer; implanting ions into a source region and a drain region; removing the photoresist layer; forming an insulating layer on the polysilicon layer; forming a gate electrode on the insulating layer; and forming a passivation layer on the insulating layer. The passivation layer covers the gate electrode. The invention can only use one time of mask process and one time of ion implantation process to complete the manufacturing processing of the polysilicon layer, the manufacturing process can be simplified and therefore the cost of process is reduced and the productivity is improved.

Floating gate transistors and method for forming the same

Abstract: A method and structure for floating gate transistors provides floating gate transistors with floating gates having sharp, well-controlled edge profiles. The sharp, well-controlled edge profiles enhance electrical functionality and endurance and are formed by a process including a planarization process that produces polysilicon segments disposed directly between adjacent STI structures, then forming a second polysilicon layer and patterning to form an upper polysilicon segment over the lower polysilicon segment to produce a combined polysilicon segment with a T-shape and having edges that overhang the adjacent edges of associated STI structures.

Method of preparing polysilicon thin film and polysilicon tft structure

Abstract: Provided is a method of preparing a polysilicon thin film and a polysilicon TFT structure, the method of preparing the polysilicon thin film comprising: Step 1: providing a substrate (1) and forming a single layer of a polysilicon thin film (3) thereon, the thickness of the polysilicon thin film (3) meeting a required thickness for manufacturing a semiconductor component; and Step 2: performing silicon ion self-implantation on the polysilicon thin film (3), a silicon ion implantation dose being less than a measurement limit that would cause the polysilicon to undergo amorphization. The method of preparing the polysilicon thin film causes implanted silicon ions to form interstitial silicon and move to a polysilicon grain boundary, enabling a reduction in polysilicon grain boundary defect density and thereby improving polysilicon thin film quality. A provided polysilicon TFT structure having an island-shaped semiconductor layer formed from a low-dose silicon ion self-implanted polysilicon thin film can reduce a grain boundary barrier in an on-state, increase carrier mobility, increase on-state current, and decrease threshold voltage, thereby improving TFT characteristics.

Investigation on the interface of polysilicon/oxide in CCD image sensors

Abstract: The morphology of interface between polysilicon and its thermal oxide is very important for the fabrication of charge-coupled device (CCD) image sensors. Poor quality of polysilicon/oxide interface may lead to leakage current, low charge transfer efficiency, image deficiency, and then reduce the product yield and device reliability. In this paper, the effects polysilicon/oxide interface morphylogy on thermal oxide breakdown characteristics of polysilicon grown by low-pressure chemical vapor deposition (LPCVD) are studied by means of scanning electron microscopy (SEM) and electrical measurement. The breakdown characteristics of the oxide are related to the polysilicon/oxide interface smoothness. As the smoothness of polysilicon/oxide interface becomes worse, the breakdown strength of thermal oxide of the polysilicon decreases. Doping process of polysilicon remarkably affects the smoothness of polysilicon/oxide interface and the breakdown strength of the oxide. Saturated doping of polysilicon improves the polysilicon/oxide interface smoothness, so the breakdown strength of polysilicon may increase.

Method of forming polysilicon gate structure in image sensor device

Abstract: A method of fabricating polysilicon gate structure in an image sensor device includes depositing a gate dielectric layer on a surface of a substrate. Then a polysilicon layer is deposited over the gate dielectric layer. Next, a protection film is deposited over the polysilicon layer. A hard mask is formed over the protection film, and the polysilicon gate structure is patterned. Following that, the hard mask is stripped off. The protection film exhibits etching selectivity against the polysilicon layer and has a thickness of between 40 and 60 angstroms. The hard mask is removed by phosphoric acid solution wet etching process.