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Showing papers on "Precision rectifier published in 2018"


Journal ArticleDOI
TL;DR: In this article, a hybrid rectifier consisting of a 12-pulse rectifier in parallel with a Vienna rectifier is presented, and a detailed analysis of how to select the output power sharing ratio based on system losses and input current distortion is presented.
Abstract: This paper presents a hybrid rectifier consisting of a 12-pulse rectifier in parallel with a Vienna rectifier. In the proposed structure, the 12-pulse rectifier supplies the bulk power to the load, whereas the Vienna rectifier shapes the input current to reduce its harmonic distortion. The unidirectional power flow of the Vienna rectifier results in undesirable distortion around the current zero crossing, which deteriorates current shaping in this region. To overcome this problem, besides current shaping, the Vienna rectifier is forced to participate in the active power. In this regard, the share of output power in each rectifier module must be calculated. To shape the input current, the reference current for the Vienna rectifier is generated using instantaneous power theory, and current tracking is carried out using the finite control set model predictive control. A detailed analysis of how to select the output power sharing ratio based on system losses and input current distortion is presented. The theoretical analysis is verified by using simulation and experimental results obtained from a 1 kW laboratory setup.

52 citations


Journal ArticleDOI
TL;DR: A microwave rectifier is presented using a novel impedance matching technique to extend the operating bandwidth using the impedance control at two separated frequencies, capable of manipulating the impedance over a wide frequency band by three steps.
Abstract: This brief presents a microwave rectifier using a novel impedance matching technique to extend the operating bandwidth. Originated from the impedance control at two separated frequencies, the matching network is capable of manipulating the impedance over a wide frequency band by three steps. In this way, the operating bandwidth is extended. Theoretical analysis is carried out and closed-form design equations are derived. For validation, a wideband rectifier is implemented operating at 0.57–0.90 GHz at the input power of 12.8 dBm. It exhibits the fractional bandwidth of 44.9% for RF-dc conversion efficiency of higher than 70%. Moreover, the rectifier keeps more than 50% efficiency within 0.57–0.90 GHz at the input power from 3 dBm to 14.1 dBm.

46 citations


Journal ArticleDOI
TL;DR: In this article, a three-phase active rectifier topology was proposed for bipolar dc distribution, which can achieve the independent dc-pole control, with only one two-level voltage source converter and an ac-side grounding inductor.
Abstract: A new three-phase active rectifier topology is proposed for bipolar dc distribution, which can achieve the independent dc-pole control, with only one two-level voltage source converter and an ac-side grounding inductor. The averaged large-signal model and linearized small-signal model of the rectifier are derived in the stationary reference frame. Moreover, a control system is proposed with proper controller parameters. Besides, the rectifier is tested on an experiment platform. Comprehensive experiment results are given and analyzed to validate the function of the proposed rectifier under different operation conditions, including the rectifier start-up performance, rectifier dynamics with unbalanced dc loads for two poles, and rectifier dynamics with asymmetrical dc voltages for two poles. Finally, the proposed rectifier is compared with other two existing ac–dc conversion approaches, in terms of required number and rating of components as well as power losses with different load imbalance levels, which further highlight some potential benefits of the proposed topology.

34 citations


Journal ArticleDOI
TL;DR: A novel modeling methodology of Schottky diode for microwave rectifier design is proposed, to consider the effective capacitance of the diode under different status being usually ignored in previous works.
Abstract: A novel modeling methodology of Schottky diode for microwave rectifier design is proposed in this paper. The challenge was to consider the effective capacitance of the diode under different status being usually ignored in previous works. In addition, the charging and discharging behaviors causing extra power consumption had been considered for a higher modeling accuracy. To improve the diode modeling, Kirchhoff current and charge conservation law are utilized to analyze the charge and discharge effects and synthesize the corresponding close-form equations. Based on these equations, once the diode model, operating frequency, output dc current are determined, the optimal performance prediction for the diode, load value selection, and impedance matching design can be implemented accordingly. For validation, the proposed modeling methodology is compared with the commercial simulation software advanced design system and other related works. For further verification, a compact single diode rectifier operating at 5.8 GHz is designed, fabricated, and measured. Good agreement between the calculated, simulated, and measured data can be obtained, demonstrating the effectiveness of proposed method.

32 citations


Journal ArticleDOI
TL;DR: In this paper, the fundamental effects of electrical loads containing non-resistive components (e.g., rectifiers and capacitors) on electromagnetic energy harvester performance were investigated.

21 citations


Journal ArticleDOI
TL;DR: In this paper, a variable switching frequency PWM (VSFPWM) strategy was proposed for dc-link voltage ripple control in two-level rectifier. But, the voltage ripple is determined by the DC-link current directly, and can be predicted synchronously with PWM signals.
Abstract: The switching frequency is an important control parameter of pulse-width-modulation (PWM) rectifier to reduce switching losses and electromagnetic interference noise. This paper proposed a variable switching frequency PWM (VSFPWM) strategy for dc-link voltage ripple control in two-level rectifier. DC-link voltage ripple is determined by the dc-link current directly, and can be predicted synchronously with PWM signals. A real-time prediction model of dc-link voltage ripple is derived for a common voltage-oriented control PWM rectifier. Then, VSFPWM control is introduced, which changes the switching frequency cycle to cycle with a restriction of dc-link voltage ripple peak value. Furthermore, the dynamic behavior is also observed when the proposed VSFPWM control scheme is adopted. Detail simulation and experimental comparisons are carried out between VSFPWM and normal constant switching frequency PWM, which demonstrate the advantages of the proposed method.

21 citations


Journal ArticleDOI
TL;DR: A novel full-wave precision rectifier circuit employing a single EXCCII, a MOS switch and one resistor is proposed, which provides rectification for a wide range signal amplitudes of −150 mV to 150’mV.
Abstract: A novel full-wave precision rectifier circuit employing a single EXCCII, a MOS switch and one resistor is proposed. The proposed voltage-mode full-wave precision rectifier is simple and operates with a supply voltage of ±1.25 V. The circuit provides rectification for a wide range signal amplitudes of −150 mV to 150 mV. The proposed circuit is easily adapted as an extended application in ASK and BPSK generation. Non-idealities of building blocks and parasitic effects are analyzed, Simulations using 0.25 µm parameters are given and comparisons drawn with most recent works, to support the new proposed circuit.

20 citations


Journal ArticleDOI
TL;DR: In this article, a low power versatile current-mode rectifier is proposed, which employs only a dual-output second-generation current conveyor (DO-CCII) and a core rectifying circuit consisting of twelve MOS transistors.
Abstract: In this paper, a new low-power versatile current-mode rectifier is proposed. As a salient feature, the proposed rectifier provides two positive half-wave, two inverting negative half-wave or two full-wave outputs from the same configuration. The proposed circuit employs only a dual-output second-generation current conveyor (DO-CCII) and a core rectifying circuit consisting of twelve MOS transistors. The input and output signals are current. Favorably, by adding two additional transistors, the proposed rectifier can also rectify voltage signals with electronic tuning capability. The simple and MOS only structure of the proposed circuit is highly attractive from integration point of view. In spite of providing multiple outputs at the same time, the proposed rectifier enjoys low power consumption. PSPICE simulations using 0.18 μm CMOS parameters and supply voltage of ±0.9 V demonstrate a precise operation and good temperature stability.

18 citations


Journal ArticleDOI
TL;DR: A new space vector modulation, i.e., ZSVM3, for three-phase quasi-Z-source rectifier (qZSR) is proposed and the operation principle of the qZSR is analyzed in detail, and the calculated value of the quasi- Z-source inductor is given.
Abstract: A new space vector modulation, i.e., ZSVM3, for three-phase quasi-Z-source rectifier (qZSR) is proposed. All switches in the three-phase bridge can be turned on and turned off with zero current or zero voltage using the proposed ZSVM3 with no auxiliary circuit. The current through the inductors of the quasi-Z-source network operates in a boundary conduction mode or discontinuous conduction mode to achieve all freewheeling diodes turned off with zero-current switching (ZCS). At the same time, the switch in the quasi-Z-source network can be turned on with ZCS. Besides, the voltage stress of all switches is equal to dc-link voltage. The operation principle of the qZSR is analyzed in detail, and the calculated value of the quasi-Z-source inductor is given. The proposed theory in this paper is verified by a 2-kW prototype.

15 citations


Journal ArticleDOI
TL;DR: In this paper, the authors presented a two-channel integrated circuit (IC) designed in Austria Mikro Systeme 350-nm technology dedicated for the silicon photomultiplier (SiPM) based applications.
Abstract: Thanks to its compact structure, mechanical endurance, and low bias voltage, the silicon photomultiplier (SiPM) can be used in small-size applications which require reduced power consumption. In order to detect the light intensity as low as a single photon, the front-end electronics has to amplify and shape the signal of the photodetector. The low-power design cannot impair the performance of readout electronics or limit the capabilities of the SiPM itself. This paper presents a two-channel integrated circuit (IC) designed in Austria Mikro Systeme CMOS 350-nm technology dedicated for the SiPM-based applications. The input stage is a super-common-gate architecture. Each channel of the IC consists of an amplifier and a peak detector with an offset reduction circuit. The power consumption of the single channel is less than 3 mW from the single voltage supply (3.3 V). Moreover, the number of channels of the IC can be easily increased thanks to small dimensions of the circuit. This paper presents a detailed analysis of the IC including: noise performance with adjustment of the input transistor’s size, transient and dc simulations of the amplifier and the peak detector, and the introduction of a simple offset reduction technique for the peak detector. The measurement results obtained with two SiPM detectors are presented.

12 citations


Journal ArticleDOI
TL;DR: In this article, different analog signal processing applications such as inverting amplifier, non-inverting amplifier, summer, subtractor, differentiator, integrator, half-wave and full-wave rectifiers, clipper, clamper, inverting and noninverting comparators, peak detector, and zero crossing detector are implemented using low-power folded cascode operational amplifier (op-amp) implemented using CNFET.
Abstract: Carbon nanotube (CNT) is one of the embryonic technologies within recent inventions towards miniaturization of semiconductor devices and is gaining much attention due to very high throughput and very extensive series of applications in various analog/mixed signal applications of today’s high-speed era. The carbon nanotube field effect transistors (CNFETs) have been reconnoitred as the stimulating aspirant for the future generations of integrated circuit (IC) devices. CNFETs are being widely deliberated as probable replacement to silicon MOSFETs also. In this paper, different analog signal processing applications such as inverting amplifier, noninverting amplifier, summer, subtractor, differentiator, integrator, half-wave and full-wave rectifiers, clipper, clamper, inverting and noninverting comparators, peak detector, and zero crossing detector are implemented using low-power folded cascode operational amplifier (op-amp) implemented using CNFET. The proposed CNFET-based analog signal processing applications are instigated at 32 nm technology node. Simulation results show that the proposed applications are properly implemented using novel folded cascode operational amplifier (FCOA) implemented using CNFET.

Proceedings ArticleDOI
01 Nov 2018
TL;DR: A mixed mode variable gain amplifier for hearing aid application is presented and achieves a gain range of 45dB to 65dB and offers an input referred noise of 0.13µVrms, with peak SNR of 77dB and consumes a power of 172µW from 1.8V supply.
Abstract: A mixed mode variable gain amplifier for hearing aid application is presented. It consists of main amplifier stage and a gain control circuit. Based on the output of microphone, voltage levels are categorized into two gain regions and designed circuit automatically sets the close loop gain of main amplifier. Main amplifier consists of opamp with feedback resistors and gain control circuit consists of peak detector, high speed comparator and XNOR gate. Due to high speed digital control circuitry, attack and release time are as small as 60µSec which is 33 times faster than temporal resolution of human hearing. Along with preamplifier, proposed circuit achieves a gain range of 45dB to 65dB and offers an input referred noise of 0.13µVrms, with peak SNR of 77dB and consumes a power of 172µW from 1.8V supply. Circuit is designed in 0.18µm CMOS process and occupies an area of 493µm × 184µm.

Journal ArticleDOI
TL;DR: A three-level rectifier structure with flying capacitors is proposed for the dc–dc converter, which has the following advantages: low-voltage diodes could be used for high- voltage output applications, and the voltage fluctuation is lower than the conventional converter under the same modulation strategy.
Abstract: In high-voltage output applications, the rectifier diodes in the conventional full-bridge converter have to bear the whole secondary voltage of a transformer. In this paper, a three-level rectifier structure with flying capacitors is proposed for the dc–dc converter. Compared with the conventional dc–dc converter, the converter with the proposed rectifier structure has the following advantages: low-voltage diodes could be used for high-voltage output applications; due to the secondary flying capacitors, there are no voltage spikes on the rectifier diodes even if no snubber circuits are attached; not only can the leading switches realize zero voltage switching (ZVS) as the same as the conventional converters, but also the lagging switches can realize zero current switching in discontinuous-conduction mode and ZVS in continuous-conduction mode; and the rectified voltage has no zero-state voltage, it has been raised to half of the input voltage, so the voltage fluctuation is lower than the conventional converter under the same modulation strategy, and the current ripple of the filter inductor can be reduced by half. The operation principle of the proposed rectifier structure is analyzed in details, and a prototype is fabricated to verify the features of the proposed converter.

Journal ArticleDOI
TL;DR: In this paper, the reference value of the primary voltage for maximizing the transmission efficiency is calculated based on primary-side information, which is caused by power control with half active rectifier on the secondary side.
Abstract: Applying wireless power transfer (WPT) to transportation applications is one of the best solutions to overcome drawbacks of electric vehicles (EVs) due to their energy storage system. Although dynamic charging of EVs can extend their driving distance, control techniques are expected to be further developed to maintain maximum transmitting efficiency and to ensure a stable supply of energy because a dynamic WPT system has to deal with parameter variation such as distance change, load change, and so on. Since a control strategy based on signal communication between the primary side and the secondary side decreases the reliability of the system, this paper proposes a primary-side efficiency control method based on the primary current change, which is caused by power control with Half Active Rectifier on the secondary side. The reference value of the primary voltage for maximizing the transmitting efficiency is calculated based on primary-side information. Simulations and experiments demonstrated that the proposed method can achieve not only the maximum transmitting efficiency but also the desired load power. キーワード:ワイヤレス電力伝送,磁界共振結合,電力制御,効率最大化,ハーフアクティブ整流器 (Wireless power transfer, Magnetic resonance coupling, Power control, Efficiency maximization, Half active rectifier ) 1. はじめに 近年,ワイヤレス電力伝送 (Wireless power transfer : WPT) は利便性や信頼性を向上できるため,産業分野および運輸 分野だけでなく,家庭機器などの幅広い分野において注目 されている 。磁界共振結合 によるWPTは数十 cm~ 数mの距離においても高効率かつ位置ずれに強いため,電 気自動車の走行中ワイヤレス給電 (1) やインホイールモー タへのワイヤレス給電 (5) などの応用も期待されている。 これらのアプリケーションでは負荷が必要とする電力に 応じてWPTの給電電力を適切に制御する必要があるが,送 受電器の位置変動や急峻な負荷変動が生じるため,送受電 間の通信によって高速な制御信号をやり取りするような制 御系では信頼性を確保することが難しい。また,WPTにお ける伝送効率を低下させずに制御できることが望ましい。 本研究では送受電間の通信を用いることなく,所望の負荷 電力および伝送効率の最大化を同時に達成する制御手法を 提案する。受電側ではハーフアクティブ整流器 (Half Active Rectifier : HAR)を用いた電力制御 (5) を導入し,送電側で は HARの動作に基づいて変化する送電側電流を測定する ことで,伝送効率を最大化する送電側電圧の制御目標値を 計算する手法を示す。シミュレーションおよび実験によっ て所望の負荷電力および伝送効率の最大化を同時に実現で きることを示し,提案手法の有効性を検証する。 2. ワイヤレス電力伝送システム 〈2・1〉 システム構成 本研究で用いるWPTシステム を Fig.1に示す。送電側は直流電源およびフルブリッジイン バータで構成し,矩形波電圧を送電器に印加する。本研究 では S/S方式の磁界共振結合WPTを採用するため,送電側 インバータの動作角周波数 ω0 および送受電器の共振角周 波数は ω0 = 1 √ L1C1 = 1 √ L2C2 · · · · · · · · · · · · · · · · · · · · · · · · (1) を満たすように与える。 受電側では HAR を用いて整流した後,バッテリー充電 システムやモータドライブシステムを想定した定電力負荷 に接続する。ここで,S/S方式の磁界共振結合WPTを介し て定電力負荷を駆動させる場合,DCリンク電圧 Vdc は不 安定になることが知られているため ,本稿では HARを用 いて Vdc を安定化させる。 〈2・2〉 HAR の 2つの動作モード HARは下アームの 半導体スイッチの ON/OFFを制御することで動作させる。 回路構成はブリッジレス PFCコンバータと同じであるが, HARは受電側における整流動作と短絡動作の切替を目的と しており,制御手法が大きく異なる。また,S/S方式の磁界 共振結合WPT回路はイミタンス変換特性を示し ,送電側 を定電圧駆動させる場合に受電側は定電流特性となるため, HARは電流経路を常に確保しなければならない。 HARの動作モードを Fig.2に示す。Fig.2(a)のRectification modeでは下アームを OFF状態とすることで,ダイオード 整流回路と同様に整流動作を行う。このとき,WPTによる 給電電力 P は DCリンクコンデンサおよび負荷に供給され る。一方で,Fig.2(b)の Short modeでは下アームをON状態

Proceedings ArticleDOI
02 Mar 2018
TL;DR: In this paper, a modified peak detector and sample hold (PDSH) circuit is proposed for analog front-end read out chain, which is designed in 180 nm CMOS technology.
Abstract: In this paper a modified peak detector and sample hold (PDSH) circuit is proposed for analog front-end read out chain. This PDSH circuit captures the energy of a sensor output of analog read out chain. The circuit is designed in 180 nm CMOS technology. The proposed PDSH offers wide range (almost 1.8 V of wide input range) of input amplitude (from 0.5 V to 2.3 V) with maximum 10mV offset variation. Peak overshoot error is 0.9 percent for signal with high amplitude. The PDSH block also been modified to decouple the redundancy between slew rate and offset.

Patent
22 Aug 2018
TL;DR: In this article, a multichannel acoustic-emission system is designed for technical diagnostics and non-destructive testing of large-sized structures during strength tests, which includes acoustic transducer (1), preamplifier (2), channel control (8), controlled filters of upper (23) and lower (24) frequencies, main amplifier (4), resistive divider (17) consisting of resistors (25), (26), (27), three two-position keys (14), (15), (16), analog-digital (6), digital
Abstract: FIELD: measuring equipment.SUBSTANCE: multichannel acoustic-emission system is designed for technical diagnostics and non-destructive testing of large-sized structures during strength tests. Contains acoustic transducer (1), preamplifier (2), channel control (8), controlled filters of upper (23) and lower (24) frequencies, main amplifier (4), resistive divider (17) consisting of resistors (25), (26), (27), three two-position keys (14), (15), (16), analog-digital (6), digital-analog (7) converters, random-access memory (9), digital signal processor (10) output of which is connected by bi-directional bus to input of Ethernet controller (22), other input of which is connected to Ethernet network switch (21). Output of main amplifier (4) is connected to series-connected peak detector (18), integrator (20), adder (19), output of which is connected via third on-off switch (16) to comparator (5), output of which is connected to inputs of random access memory (9) and digital signal processor (10).EFFECT: such performance of system ensures its operation when changing input signals in wide dynamic range, and controlled high and low frequency filters can suppress noise and interference.1 cl, 2 dwg

Journal ArticleDOI
TL;DR: In this article, a peak detector is proposed using low voltage OTRA, which is simulated using PSPICE simulation for which OTRA is realized using 180 nm CMOS process with low power supply of + 0.9V.
Abstract: Previously, peak detector was build using diode, capacitor and a voltage mode device i.e. OpAmp. Due to emergence of current mode circuits, it is possible to design high gain, large bandwidth, high speed and low voltage analog signal processing and generating applications. OTRA (Operational transresistance amplifier) is in fashion to design these applications due to its various advantages. In this paper, peak detector is proposed using low voltage OTRA. This proposed circuit is simulated using PSPICE simulation for which OTRA is realized using 180 nm CMOS process with low power supply of +0.9V. The proposed circuit also provide very low power dissipation.

Proceedings ArticleDOI
01 Mar 2018
TL;DR: In this article, a dual-band RF-DC conversion system is designed to passively amplify the available voltage for rectification by developing a resonator with high quality factor, which is implemented using a combination of clamper and peak detector.
Abstract: Design, simulation and implementation of dual band radio frequency energy harvesting (RFEH) system operating at 900MHz and 1.8GHz is introduced. In the proposed design, RF-DC conversion system is designed to passively amplify the available voltage for rectification by developing a resonator with high quality factor. Passive amplification and rectification is implemented using a combination of clamper and peak detector. Harmonics presented in the rectified output voltage is eliminated by using matching network and filter. Energy harvesting system designed and simulated is then implemented and tested. Close agreement between analytical, simulation and measurement results are obtained.

Patent
29 Jun 2018
TL;DR: In this paper, a turn-to-turn short circuit detection in inductance coils has been investigated, where a transformer whose secondary winding is connected through the diode to the storage capacitor and to the serial circuit, consisting of a winding being checked, is connected to an electronic power switch controlled from the control unit.
Abstract: FIELD: measuring equipmentSUBSTANCE: invention relates to measuring equipment Essence: device for searching turn-to-turn short circuits in inductance coils contains a transformer whose secondary winding is connected through the diode to the storage capacitor and to the serial circuit, consisting of a winding being checked, an electronic power switch controlled from the control unit Primary winding of the transformer is connected through the electronic switch of the converter to a DC voltage source Electronic switch of the converter is controlled from the PWM output of the controller Current sensor is connected in series with the electronic power switch Current sensor output is connected via the second peak detector to the information input of the second comparator Voltage from the storage capacitor is fed through the voltage divider on the resistors and through the matching unit to the feedback input of the PWM controller, to the input of the first peak detector and to the input of the differentiator From the output of the differentiator, the voltage is fed through the rectifier ad through the third comparator to the input of the control unit Output of the first peak detector is connected to the input of the first comparator and to the reference input of the second comparator Output of the first comparator is connected to the circuit indicator and the first input of the logic unit Second input of the logic unit is connected to the output of the second comparator Output of the logic unit is connected to the indicator of turn-to-turn short circuitsEFFECT: technical result: increase in the reliability and accuracy of detecting turn-to-turn short circuits1 cl, 2 dwg

Patent
09 Mar 2018
TL;DR: In this paper, a ripple detection device consisting of a filter amplifying circuit, a peak detector, a voltage dividing and filtering circuit, voltage follower, a microprocessor and a displayer is presented.
Abstract: The invention provides a ripple detection device. The device comprises a filter amplifying circuit, a peak detector, a voltage dividing and filtering circuit, a voltage follower, a microprocessor anda displayer, wherein the filter amplifying circuit is used for collecting an alternating current component of a to-be-detected signal and performing filtering amplification on the alternating currentcomponent to obtain a to-be-detected ripple signal; the peak detector is used for detecting peak-to-peak value of the to-be-detected ripple signal to form a peak signal; the voltage dividing and filtering circuit is used for performing voltage dividing on the to-be-detected signal and filtering the to-be-detected signal to extract a voltage divided signal of the direct current component of the to-be-detected signal after voltage dividing; the voltage follower is used for isolating the microprocessor and the voltage dividing and filtering circuit and performing impedance conversion on the voltage divided signal to form a converted signal; the microprocessor is used for processing the peak signal and the converted signal to obtain a ripple voltage value and a direct current voltage value ofthe to-be-detected signal; the displayer is used for displaying the ripple voltage value and the direct current voltage value of the to-be-detected signal. Detection of the ripple voltage and the direct current voltage of a direct current stabilized voltage power supply can be realized, and performance of the direct current stabilized voltage power supply can be detected conveniently.

Patent
23 May 2018
TL;DR: In this article, a primary and secondary converters are connected by a communication line with a common shield, providing the possibility of a one-time measurement of the levels of low-frequency and high-frequency vibrations, as well as temperature.
Abstract: FIELD: metrology.SUBSTANCE: invention relates to vibrational metrology. Device for diagnosing equipment consists of a primary and a secondary converter. Primary converter contains a temperature sensor, a low-pass filter, a charge amplifier, a normalizing amplifier, an output stage, a vibration sensor, and an alternating voltage to current converter. Secondary converter contains a spark protection barrier, a buffer stage, a direct voltage to current converter, a proportional filter, a second buffer stage, a high pass filter, a bandpass filter, a peak detector, a second direct voltage to current converter, an integrator, a root mean square detector, a third direct voltage to current converter, a narrowband filter, second peak detector, average detector, logarithm, first and second buffer averaging stages, second logarithm. Vibration sensor consists of a piezo-bimorph, a bolt made of non-magnetic steel, precision washers. Case of the primary converter contains a threaded pin and a four-prong connector. Primary and secondary converters are connected by a communication line with a common shield. Temperature sensor is glued in a cylindrical recess in the inner part of the housing.EFFECT: providing the possibility of a one-time measurement of the levels of low-frequency and high-frequency vibrations, as well as temperature.8 cl, 3 dwg

Patent
Shi Zhengyu, Cheng He, Xiao Xiao, Wang Wen, Tang Zhu 
29 May 2018
TL;DR: In this paper, a negative feedback automatic gain control circuit based on neural network aims at solving the inaccurate problem that the deviation appears of gain that automatic gain controller circuit brought among the prior art because of temperature and circuit self deviation etc.
Abstract: The utility model discloses a negative feedback automatic gain control circuit based on neural network aims at solving the inaccurate problem that the deviation appears of gain that automatic gain control circuit brought among the prior art because of temperature and circuit self deviation etc. The utility model provides a neural network's input study sample includes the control voltage vc that detection voltage vp and low pass filter exported that input voltage vin, peak detector exported of whole circuit, has simulated the circuit deviation of inside each module of AGC or the operating differential that the temperature variation brought better to produce the size that more accurate reference voltage had more accurately controlled the gain, realized the gain control of high accuracy, thisapplication is applicable to the relevant field of gain control circuit.

Journal ArticleDOI
TL;DR: The proposed delay time compensation scheme boosting operational frequency to 20 MHz while delivering high-accuracy measurements of the peak voltage doubles measured performance over standard peak detectors.
Abstract: Loop delay degrades the accuracy of the traditional peak detectors and limits operational frequency to 1 MHz or less. This paper proposes a delay time compensation scheme boosting operational frequency to 20 MHz while delivering high-accuracy measurements of the peak voltage. The proposed peak detector is implemented using TSMC 0.18 $$\upmu $$ m CMOS process requiring only 1.05363 mm $$^2$$ . The new approach doubles measured performance over standard peak detectors.

Patent
Karmaker Rahul1
10 May 2018
TL;DR: In this paper, the authors describe aspects of a fast settling peak detector, which includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor.
Abstract: The present disclosure describes aspects of a fast settling peak detector. In some aspects, a peak detector circuit includes a first transistor having a gate coupled to an input of the circuit at which a signal is received and a drain coupled to a source of a second transistor. Current may flow in the first and second transistors responsive to the signal. The circuit also includes a third transistor having a gate coupled, via a signal-inverting component, to the input of the circuit and a drain coupled to a source of a fourth transistor. Through an inversion of the signal, other current flowing in the third and fourth transistor can reduce or cancel a frequency component of the current in the first and second transistors. In some cases, this precludes a need to filter the frequency component from an output of the circuit.

Patent
30 Oct 2018
TL;DR: In this paper, a continuous sinusoidal signal transmitting circuit of difference frequency, including the transmitting circuit, is used for producing the transmission signal on the transmission output of transmission circuit, DDS frequency synthesizer, it is used to generate a plurality of, as to have the different frequency continuous ssinoidal voltage signals, the oval low pass filter in seven rank, it was used for the filtering clutter, obtains pure, the regular continuous sisoidal voltage signal of output, voltage amplifier, adjusted the magnitude of voltage of post-filter, power amplifier, its power that
Abstract: The utility model relates to a continuous sinusoidal signal transmitting circuit of difference frequency, including the transmitting circuit, it is used for producing the transmission signal on the transmission output of transmitting circuit, DDS frequency synthesizer, it is used for generating a plurality of, as to have the different frequency continuous sinusoidal voltage signals, the oval low pass filter in seven rank, it is used for the filtering clutter, obtains pure, the regular continuous sinusoidal voltage signal of output, voltage amplifier, it is used for the amplified voltage signalamplitude, adjusts the magnitude of voltage of post -filter, power amplifier, its power that is arranged in the regulating circuit, the clock circuit, its synchronization that is used for realizing binary channels DDS frequency synthesizer, peak detector, it is used for realizing the balance between the binary channels transmitting circuit, the network matching, it is used for carrying out dynamic impedance with the transducer and matches, and the drive transducer produces the continuous acoustic signals of required frequency. The utility model discloses can regard as the independent ultrasonic signal driving source in ultrasonic wave nondestructive test field, and the circuit operation is stable, the reliability is high, and the using value is high.

Book ChapterDOI
01 Jan 2018
TL;DR: The performance issues pertaining to input currents, power factor, and commutation problems in control rectifier are addressed and the various topologies pertaining to active rectification are presented.
Abstract: In this chapter, the various topologies of single-phase controlled rectifier are presented. In the first part of the chapter, topologies pertaining to low switching frequency such as half-wave, biphase, and full-wave rectifier with source inductance are presented. In the later parts, the various concepts and topologies pertaining to active rectification are presented. The performance issues pertaining to input currents, power factor, and commutation problems in control rectifier are addressed. The various topologies of unity-power-factor rectifiers, synchronous rectifiers, and rectifier using matrix converter are presented.

Patent
02 Mar 2018
TL;DR: In this article, an asynchronous peak detector consisting of an analogue input (1) and an analogue output (2), the first (3) precise rectifier, the first 6 storage capacitor, the second 7 storage capacitor and the second 10 storage capacitor are used as matching stages.
Abstract: FIELD: measuring equipment.SUBSTANCE: asynchronous peak detector comprises an analogue input (1) and an analogue output (2), the first (3) precise rectifier, the first (6) storage capacitor, the second (7) precise rectifier, the second (10) storage capacitor, the first (11) electronic key, the second (12) electronic key, a pulse signal control generator (17), the first (18) matching stage, the second (19) matching stage. The additional precise rectifiers (18) and (19), whose outputs (20) and (21) are connected with the analogue output of the device (2), are used as the first (18) and second (19) matching stages, wherein the first (11) and second (12) electronic keys ensure shutdown of the first (3) and second (7) precise rectifiers during the discharge time of the first (6) and second (10) storage capacitors.EFFECT: increased reliability of the asynchronous peak detector in the discharge mode of the storage capacitors.3 cl, 9 dwg

Patent
07 Nov 2018
TL;DR: In this paper, the authors proposed a method to increase the noise immunity of a seismic non-contact human detector from seismic interference of various origins with an increase in the reliability of detecting a moving person.
Abstract: FIELD: measuring equipment; data processing.SUBSTANCE: invention relates to seismic non-contact human detectors. Seismic non-contact human detector contains a sequentially connected geophone, a preamplifier, a bandpass filter, an amplifier, a rectifier integrator, a first threshold device, a step classifier, an OR gate, a counter and an actuator, wherein the second counter input is connected to the second output of the step classifier and the input of the time device, the output of the temporary device is connected to the second input of the OR gate and the first threshold device comprises an additional output which is connected to an input of an automatic gain control circuit whose output is connected to the second input of the amplifier. Output of the integrator rectifier is connected to the input of the differentiator and the input of the first peak detector, while the output of the differentiator is connected to the input of the second peak detector, and the output of the first peak detector and the output of the second peak detector are connected to the inputs of the ratio calculation unit, in addition, the second threshold device, the XOR gate and the AND gate are connected in series to the output of the ratio calculation unit, and the AND gate is embedded in the connection of the second output of the step classifier with the second input of the counter and the input of the temporary device.EFFECT: invention makes it possible to increase the noise immunity of a seismic non-contact human detector from seismic interference of various origins with an increase in the reliability of detecting a moving person.1 cl, 1 dwg

Patent
16 Mar 2018
TL;DR: In this paper, an attenuation amplitude adjustable low frequency power amplifier is proposed, which consists of a low noise amplifier, bandstop filter, a signal amplifier, a power amplifier, the peak detector, an analog to digital converter, a microcontroller, an LCD display, a voltage stabilized power supply and a load.
Abstract: The invention discloses an attenuation amplitude adjustable low frequency power amplifier, comprising a low noise amplifier, a bandstop filter, a signal amplifier, a power amplifier, a peak detector,an analog to digital converter, a microcontroller, an LCD display, a voltage stabilized power supply and a load. The low noise amplifier, the bandstop filter, the signal amplifier, the power amplifier, the peak detector, the analog to digital converter, the microcontroller and the LCD display are connected in sequence. The low noise amplifier receives an input signal. The load is connected with the power amplifier. The voltage stabilized power supply supplies power to the low noise amplifier, the bandstop filter, the signal amplifier, the power amplifier, the peak detector, the analog to digital converter, the microcontroller and the LCD display. The attenuation amplitude adjustable low frequency power amplifier is simple in circuit structure and chip in device price. According to the attenuation amplitude adjustable low frequency power amplifier, a low frequency signal can be amplified well; relatively high indexes and relatively high practicability can be achieved in aspects such asan output bandwidth, power and efficiency; and the interference of power frequency noise can be effectively filtered.

Proceedings ArticleDOI
01 Nov 2018
TL;DR: The IDeF-X HDBD as discussed by the authors is a 32-channel application specific integrated circuit designed to read charges ranging from -40 to 40 fC. This circuit has been designed with radiation mitigation techniques allowing it to handle a dose up to 300 krad and a Single Event Latchup (SEL) threshold of 65 MeV.
Abstract: IDeF-X HDBD is the new version of a family of integrated circuits dedicated to the readout of semiconductor detectors. It is a 32-channel Application Specific Integrated Circuit designed to read charges ranging from -40 to 40 fC. The circuit was optimized for small detector capacitances (<1pF) and low leakage current (<1nA). The chip allows to reach an Equivalent Noise Charge floor (ENC) of 17 el.rms. It has a self-triggering capability allowing multiple types of readout either only hit channels, selected channels or all channels. Each channel is based on a scaled charge sensitive amplifier follower by a CR-RC² filter and a peak detector with a pile-up rejection system allowing memorizing only the first arriving charge. Each channel has a power consumption of 850 µW. Gain and shaping time are tunable. This circuit has been designed with radiation mitigation techniques allowing it to handle a dose up to 300 krad and a Single Event Latchup (SEL) threshold of 65 MeV.cm²/mg suitable for space applications. This ASIC can read either Cadmium Telluride or Silicon detectors for instance for imaging-spectroscopy applications.