Showing papers on "Snapback published in 2000"

Single-event upset and snapback in silicon-on-insulator devices and integrated circuits

Abstract: The characteristics of ion-induced charge collection and single-event upset are studied in silicon-on-insulator (SOI) transistors and circuits with various body tie structures. Impact ionization effects, including single-event snapback, are shown to be very important. Focused ion microbeam experiments are used to find single-event snapback drain voltage thresholds in n-channel SOI transistors as a function of device width. Three-dimensional device simulations are used to determine single-event upset and snapback thresholds in SOI SRAMs, and to study design tradeoffs for various body-tie structures. A window of vulnerability to single-event snapback is shown to exist below the single-event upset threshold. The presence of single-event snapback in commercial SOI SRAMs is confirmed through broadbeam ion testing, and implications for hardness assurance testing of SOI integrated circuits are discussed.

Apparatus for providing high performance electrostatic discharge protection

Abstract: Apparatus for providing electrostatic discharge protection having an nMOS transistor with bias simultaneously applied to the gate and the p-well of the nMOS transistor. A bias circuit is fabricated using a plurality of the Zener diodes. The double bias allows for a relatively high gate voltage to be applied to the nMOS transistor enabling the nMOS transistor to be biased to optimum conditions for bipolar snapback.

High voltage ESD protection device with very low snapback voltage by adding as a p+ diffusion and n-well to the NMOS drain

Abstract: A device layout is disclosed for an ESD device for protecting NMOS high voltage transistors where the SCR protection device and the two NMOS transistors are integrated. The two NMOS transistors share an n-type doped drain (ndd) area which has implanted two n+ drains, one for each of the two transistors and a p+ diffusion separates the two n+ drains. Furthermore, the ndd area has implanted an n-well which extends from halfway under the first n+ drain to halfway under the second n+ drain. In addition, the depth of the n-well exceeds the depth of the ndd area. The added p+diffusion together with the ndd area and the p-substrate of the silicon wafer create the parasitic pnp transistors of the SCR. The shared ndd area together with the n+ sources of the NMOS transistors creates the SCR's two parasitic npn transistors. The low triggering voltage of the SCR is achieved by the combination of the n-well, the ndd area, the p+diffusion between the two drains, and by having the two parasitic npn transistors paralleled.

Electrical-thermal coupling mechanism on operating limit of LDMOS transistor

Abstract: The continuing march for reduction of feature size and enhancement of the functional integration is now seriously challenged by the limited capability in handling increased power dissipation, not only in power electronics but also in the field of VLSI and ULSI. Interaction between the electrical and thermal energy generated by self-heating is fundamental in understanding this power dissipation limit and safe operating area (SOA) of the semiconductor devices in both transient and steady-state operations. This work treats the problem of the electrical-thermal coupling (ETC) phenomena based on a LDMOS device through theoretical and experimental analyses. This report discusses an ETC driven snapback breakdown, "Hot-snapback", to explain the decrease in SOA, both voltage and current. The "Hot-snapback" process is much more favorable for explaining the device failure mechanism typically observed at the center of the thermal mass than the "intrinsic junction temperature" theory.

A fast sextupole probe for snapback measurement in the LHC dipoles

Abstract: In superconducting particle accelerators a fast change of the magnetic field occurs during the first few seconds after the start of an energy ramp. Standard magnetic measurements using a coil rotating at 1 Hz do not have the time resolution required to completely resolve this phase, usually called snapback. For this reason we have developed a new and fast system dedicated to sextupole measurements. The basic component consists of three Hall plates mounted on a ring. In an ideal case this arrangement compensates the main dipole field and produces a signal proportional to the sextupole only. Mechanical tolerances and differences in the sensitivity of the Hall plates are compensated by instrumentation amplifiers and an in situ fine adjustment of the probe orientation. Using this hybrid compensation technique we have measured sextupole variations in an LHC dipole prototype during snapback at a rate of 5 Hz. In this paper we present details on the device and the results of our measurements.

Internally triggered electrostatic device clamp with stand-off voltage

Abstract: An ESD protection device including a compound transistor structure having a trigger transistor and an ESD protection transistor. The trigger transistor includes a breakdown potential between the standoff voltage of a circuit to be protected and the breakdown potential of the ESD protection transistor. When activated, the trigger transistor operates to turn on the ESD protection transistor that is designed to carry the bulk of the conduction current associated with an ESD event. The trigger transistor is designed with an internal gain mechanism to ensure that it will not be turned off when a modified snapback voltage is reached during the ESD protection transistor operation. The trigger transistor is a minor contributor to the conducting current with the ESD protection transistor after such time as protection circuit operation acts. A process for fabricating a suitable compound transistor structure is disclosed.

Analysis and compact modeling of a vertical grounded-base NPN bipolar transistor used as an ESD protection in a smart power technology

Abstract: A thorough analysis of the physical mechanisms involved in a vertical grounded-base NPN bipolar transistor (VGBNPN) under ESD stress is first carried out by 2D-device simulation, square pulse measurements (TLP) and photoemission experiments. As a result, we propose a compact model using a new physics-based avalanche formulation. This allows reproduction of the unexpected low value of the VGBNPN snapback holding voltage under TLP stress.

Gate electrode controllable electrostatic discharge (ESD) protection structure having a MOSFET with source and drain regions in separate wells

Abstract: An ESD protection structure for use with ICs that can protect from ESD events of both positive and negative polarities, has a low snapback holding voltage and a high maximum snapback current, and is relatively immune to thermal overheating. The structure includes a semiconductor substrate of a first conductivity type (typically P-type), as well as first and second well regions of a second conductivity type (typically N-type) that are separated a gap region of the first conductivity type and disposed in the substrate. A gate silicon dioxide layer overlies the gap region and a gate electrode overlies the gate silicon dioxide layer. Also included are first and second floating regions (of the second conductivity type) disposed in the first and second well regions adjacent to the gap region, respectively. The structure further includes first and second contact regions of the first conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively. Also included are first and second contact regions of the second conductivity type disposed on the first and second well regions, respectively, and spaced apart from the first and second floating regions, respectively. During operation, the structure undergoes low current avalanche breakdown of the gap region between the first and second floating regions, followed by “double injection” of both holes and electrons. The structure's symmetrical nature provides for protection from both positive and negative ESD events and the gate electrode provides breakdown control capability.

Electrostatic discharge protection device for mixed voltage application

Abstract: A novel electrostatic discharge (ESD) protection device used for mixed voltage application is disclosed. A primary ESD device and a MOS transistor stack are respectively coupled to the input/output pad. The MOS transistor stack is formed in a cascode configuration comprising a first MOS transistor and a second MOS transistor form in different active areas. The drain region of the first MOS transistor is coupled to the input/output pad and the gate region is coupled to a low power supply. The second drain region of the second MOS transistor is coupled to the source region of the first MOS transistor, while the gate region and the source region grounded. The primary ESD device is selected with a junction breakdown voltage no more than the lowest junction breakdown voltage of the MOS transistor stack, so that the primary ESD device enters snapback prior to the MOS transistor stack.

Investigation of Body-Tie Effects on Ion Beam Induced Charge Collection in Silicon-On-Insulator FETs Using the Sandia Nuclear Microprobe

Abstract: Silicon-on-insulator (SOI) technology exhibits three main advantages over bulk silicon technology for use in radiation environments. (1) SOI devices are immune to latchup, (2) the volume of the sensitive region (body) and hence total charge collection per transient irradiation is much reduced in SOI devices and (3) the insulating layer blocks charge collection from the substrate (i.e., no funneling effect). This effectively raises the single event upset (SEU) threshold for the SOI device. However, despite their small active volume SOI devices are still vulnerable to single event effects (SEE). Inherent in the SOI transistor design is a parasitic npn bipolar junction transistor (BJT), where the source-body-drain acts as an emitter-base-collector BJT. An ion strike to a floating (not referenced to a specific potential) body creates a condition where the excess minority carriers in the drain-body cause the parasitic BJT to turn on and inject more charge into the drain than was deposited in the device by the ion. In extreme cases the floating body effect (FBE) can trigger a high-current state called single-event snapback (SES) where channel conduction is sustained indefinitely through regenerative electron-impact ionization near the drain junction. Tying the body to the source limits the emitter-base current and reduces the sensitivity of the device to single ion strikes. Unfortunately, the body-tie loses effectiveness with distance due to resistivity, and in regions far enough from the tie the BJT is still in effect. Using the Sandia nuclear microprobe we have created charge collection maps on Sandia CMOS6rs SOI FETs of varying channel widths. These devices have body ties at both ends of the channel region. Results clearly demonstrate that distance of the ion strike from the body tie has an inverse effect upon charge collection and SES sensitivity due to the resistivity of the channel. Experimental results compare well with DAVINCI simulations and electrically induced snapback thresholds. In addition, an interesting saturation effect of SES versus the amount of injected charge is observed.

Single-event upset and snapback in silicon-on-insulator devices

Abstract: SEU is studied in SOI transistors and circuits with various body tie structures. The importance of impact ionization effects, including single-event snapback, is explored. Implications for hardness assurance testing of SOI integrated circuits are discussed.

Floating body ESD protection circuit

Abstract: A floating body ESD protection circuit positioned between and coupled to an I/O pad and an internal circuit. A p-type depletion mode transistor is used to control the body of an n-type enhancement mode transistor. When the p-type depletion mode transistor is triggered, the body of n-type enhancement mode transistor remains grounded. If the p-type depletion mode transistor has not been triggered, the body remains in a floating state, lowering the range of the snapback voltage. As a consequence the ESD protection circuit is able to function more rapidly. Similarly, an n-type depletion mode transistor is used to control the body of a p-type enhancement mode transistor. When the n-type depletion mode transistor is triggered, the body remains coupled to a high voltage. If the n-type depletion mode transistor has not been triggered, the body is in a floating state. Thus, the range of the snapback voltage can be lowered, enabling the ESD protection circuit to function more rapidly.

Electrostatic protective element circuit, semiconductor device having the same and manufacture thereof

Abstract: PROBLEM TO BE SOLVED: To increase the electrostatic protective capability by making the concentration of a well below a channel formation region of an N-type MOS transistor included in an electrostatic protective element circuit lower than that of a well below a channel formation region of an N-type MOS transistor included in other circuit than the electrostatic protective element circuit. SOLUTION: On a P-type semiconductor substrate 1, a P-type well 2 having a concentration of 3×1017 (atoms/cm3) or about is formed. Right under a gate electrode 6, a low concentration P-type impurity region 3 having a concentration of 1×1016 (atoms/cm3) or about which is for improvement of a snapback characteristic and has a lower a concentration than the P-type well 2, and a P-type impurity region 4 for adjusting Vt having the a concentration of 5×1017 (atoms/ cm3) or about which is higher than the concentration of the lower density P-type impurity region 3, are formed. Moreover, a gate oxide film 5, a gate electrode 6, and the source and the drain 7 are formed to build an N-type MOS transistor 20. As a result, the electrostatic protective capability can be increased.

Comparison of flight and ground data for radiation-induced high current states in the 68302 microprocessor

Abstract: It has been observed that the 68302 microprocessor, which is being flown on several space vehicles, has not shown signs of experiencing either single event latchup (SEL) or single event snapback (SES) as would have been predicted using ground-based test data. This study presents the comparison of the flight to ground data.

Sextupole snapback detector

Abstract: At the European Organisation for Nuclear Research a new accelerator, the Large Hadron Collider (LHC),is under construction. Superconducting magnets will guide the beam, and this technique implies ...

Semiconductor device and method for reducing parasitic bipolar effect in electrostatic discharge

Abstract: PROBLEM TO BE SOLVED: To provide a circuit and a method which reduce parasitic bipolar effect during electrostatic discharge. SOLUTION: A circuit 20 contains a resistor 26 and a current source 32 increasing a source voltage of an N-channel transistor, prevents forward direction bias of a voltage between a base and an emitter of a parasitic bipolar element, and prevents electric conduction in the parasitic bipolar element. For example, comparatively small resistance 26 is connected between a source and a ground of the N-channel transistor 24. By using a current source 32, a part of an ESD current from positive ESD event is made to flow in the small resistor 26, a source voltage of the N-channel transistor 24 is increased during the event, and snapback of the parasitic bipolar element is prevented.

Electrostatic discharge circuit

Abstract: PURPOSE: An ESD(electrostatic discharge) circuit is provided to improve a performance of electrostatic discharging by occurring a fast snapback using a field transistor CONSTITUTION: A semiconductor substrate is defined by a field oxide(12) to an active region and a field region An NMOS transistor(20) comprises a first gate(13a) formed on the active region and a first contact part(14a) formed at both sides of the first gate A field transistor(30) includes a second gate(13b) formed on the field region and a second contact part(14b) formed at both sides of the second gate(13b) The first gate(13a) and the second gate(13b) are connected to an internal circuit(16) through a first wire(17), and the first contact part(14a) and the second contact part(14b) are connected to a pad(15) via a second wire(18)

The Mechanism Responsible for a Low Electrostatic Discharge Failure Threshold of an Output Buffer Circuit with Low Current Drive Capability

Abstract: The electrostatic discharge (ESD) failure threshold of an output buffer is observed to be sensitive to the used-gate finger number. It is found that the lower the current drive capability, the lower the ESD failure threshold, and the damage sites of the output buffer are always located at the used gate n-channel metal-oxide semiconductor (NMOS) transistors. This observation can only be explained on the basis of the energy dissipation (E=VSP×ID×time) in each finger, where ID is composed of channel current and bipolar current. From the real-time current-voltage measurement during ESD zapping, three phenomena are observed. The first is that a transistor with a floating gate (used-gate fingers) has a larger snapback voltage (VSP) than that with a grounded gate transistor. The second is that due to the accumulation of hot holes in the floating gate, a constant gate voltage can be induced during the ESD zapping. The last is that this induced-gate-voltage can assist the switching on of the NMOS transistors and reduction of the ESD duration. Therefore, the ESD duration of a transistor with high current drive capability will be much shorter than that of low current drive capability. As a result, high current drive capability leads to a high ESD failure threshold.

Advanced integrated process and ESD protection structure to optimize the GOI, HCE, and ESD performance for subquarter micron technology

Abstract: In this study, the super-steep retrograde N-channel doping profile was found to degrade the gate oxide integrity (GOI), hot carrier lifetime and the ESD performance. Therefore, a simple method was proposed to from the conventional -channel doping profile without adding the masking step. In addition, to improve the oxide/Si interface quality, a modified LDD structure with As and P 31 co-implant followed by gate re-oxidation was also proposed to improve the hot carrier lifetime. To improve the ESD failure threshold, after the real-time I-V characteristics measurement during ESD zapping event and detail failure analysis, a modified multi-finger protection structure with P+ diffusion into source regions was also proposed to relieve the current crowding effect. Moreover, for reducing the snapback voltage, a P- type dopant was proposed to implant into the drain region of the ESD transistor.