Showing papers on "Snapback published in 2012"

Charge pump electrostatic discharge protection

Abstract: Techniques for electrostatic discharge (ESD) protection for amplifiers and other circuitry employing charge pumps. In an exemplary embodiment, a Vneg switch coupling a second flying capacitor node to a negative output voltage node is closed in response to an ESD event being detected between a supply voltage node and the negative output voltage node. A ground switch coupling a ground node to the second flying capacitor node is closed in response to an ESD event being detected between the ground node and the negative output voltage node. The Vneg switch is further closed in response to the ESD event being detected between the ground node and the negative output voltage node. Further techniques are disclosed for providing on-chip snapback clamps at the output of a power amplifier coupled to the charge pump to protect against ESD events as defined by the standard IEC 61000-4-2.

A Snapback Suppressed Reverse-Conducting IGBT With a Floating p-Region in Trench Collector

Abstract: A novel reverse-conducting insulated-gate bipolar transistor (RC-IGBT) featuring an oxide trench placed between the n-collector and the p-collector and a floating p-region (p-float) sandwiched between the n-drift and n-collector is proposed. First, the new structure introduces a high-resistance collector short resistor at low current density, which leads to the suppression of the snapback effect. Second, the collector short resistance can be adjusted by varying the p-float length without increasing the collector cell length. Third, the p-float layer also acts as the base of the n-collector/p-float/n-drift transistor which can be activated and offers a low-resistance current path at high current densities, which contributes to the low on-state voltage of the integrated freewheeling diode and the fast turnoff. As simulations show, the proposed RC-IGBT shows snapback-free output characteristics and faster turnoff compared with the conventional RC-IGBT.

An Investigation of a Novel Snapback-Free Reverse-Conducting IGBT and With Dual Gates

Abstract: A novel reverse-conducting insulated-gate bipolar transistor (RC-IGBT) with an automatically controlled anode gate, named AG-RC-IGBT, is proposed in this paper, wherein a gate on the reverse IGBT is intrinsically off in the forward conduction state and can be automatically turned on in the reverse conduction state. Therefore, bidirectional conduction capability with snapback-free characteristics is achieved in the novel RC-IGBT. Depending on the parameters set on the reverse IGBT, its operation mode can be either like an antiparallel IGBT or like an antiparallel MOS-controlled thyristor (MCT). The antiparallel MCT mode can yield low snapback current densities and low on-state voltages in both forward and reverse conductions. Two-dimensional numerical simulations show that snapback-free characteristics are obtained in the AG-RC-IGBT antiparallel with an IGBT by a 15-μm-wide half-pitch in both forward and reverse conduction states. The antiparallel MCT mode achieves low on-state voltages of 0.97 and 1.6 V at the current density of 200 A/cm2 in reverse and forward conduction states, respectively.

Selector for low voltage embedded memory

Abstract: Techniques, materials, and circuitry are disclosed which enable low-voltage, embedded memory applications. In one example embodiment, an embedded memory is configured with a bitcell having a memory element and a selector element serially connected between an intersection of a wordline and bitline. The selector element can be implemented, for instance, with any number of crystalline materials that exhibit an S-shaped current-voltage (IV) curve, or that otherwise enables a snapback in the selector voltage after the threshold criteria is exceeded. The snapback of the selector is effectively exploited to accommodate the ON-state voltage of the selector under a given maximum supply voltage, wherein without the snapback, the ON-state voltage would exceed that maximum supply voltage. In some example embodiments, the maximum supply voltage is less than 1 volt (e.g., 0.9 volts or less).

Bipolar snapback in junctionless transistors for capacitorless dynamic random access memory

Abstract: In this work, we analyze the snapback effect and extract the effective bipolar current gain in junctionless nanotransistors. The optimal electron and hole concentrations required to trigger and sustain bipolar snapback in junctionless transistors have been evaluated. The occurrence of snapback at lower drain bias (≅ 2 V) in junctionless devices in comparison to conventional inversion mode transistors demonstrates the enormous potential for static power reduction in capacitorless dynamic random access memories. High values (40–70) of effective bipolar current gain achieved in optimally designed junctionless transistors can be utilized to improve the sensing margin for dynamic memories.

Esd protection circuit

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second pads to protect an internal circuit therebetween Under a normal operating condition, a voltage on the first pad is higher than that on the second pad The ESD protection circuit includes a substrate of a first conductivity type; first well of a second conductivity type in the substrate, wherein the first well is coupled to the first pad; a snapback device housed in the first well; and a diode string in the substrate, connected in series with the snapback device and separated from the first well, wherein the serially connected diode string and snapback device is connected between the first pad and the second pad With the isolation from the first well, the holding voltage of the ESD protection circuit can be tuned by adjusting the number of diodes in the diode string without using a guard ring

Tile-level snapback detection through coupling capacitor in a cross point array

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for tile-level snapback detection through a coupling capacitor in a phase-change memory array. Other embodiments may be described and claimed.

A physically-based behavioral snapback model

Abstract: This paper presents an accurate and robust model for snapback in ESD clamps. Impact ionization, which triggers snapback, takes time to occur; our model introduces a behavioral time-dependent low resistance on-state current that, like real devices, smoothly and continuously turns on and off, thereby eliminating convergence issues during simulation.

Latch-up free rc-based nmos esd power clamp in hv use

Abstract: An RC-based electrostatic discharge protection device provides an extended snapback trigger voltage range, thereby avoiding latch-up Two parallel current discharge paths are provided between supply terminals during an electrostatic discharge event by virtue of an added external resistor The first current discharge path includes body resistance of the protection device and the second current discharge path includes the external resistor

A Snapback Suppressed Reverse Conducting IGBT with Oxide Trench Collector

Abstract: A novel reverse conducting insulated-gate bipolar transistor (RC-IGBT) is proposed and investigated by numerical simulations. This new device features an oxide trench inserted between the N-collector and the P-collector. The oxide trench increases the collector short resistance by cutting off the low resistance electron path which is formed by the N-buffer layer. The snapback effect is therefore suppressed. Furthermore, the collector short resistance can be adjusted by varying the depth of oxide trench without dramatically increasing the collector cell dimension. As simulation results show, the snapback can be completely eliminated with 240-μm-length collector cell and integrated free-wheeling diode (FWD) with about 0.8-V on-state voltage at collector current density of 100 A/cm2. It is worth to point out that the new structure makes the P-collector/N-buffer junction current relatively uniform, which is favorable to the device reliability.

A semiconductor device comprising an esd protection device, an esd protection circuitry, an integrated circuit and a method of manufacturing a semiconductor device

Abstract: A semiconductor device includes an ESD protection device. In a N-well, two P+ doped regions form a collector and emitter of a parasitic transistor of the ESD protection device. The N-well area between the P+ doped regions, forms a base of the parasitic transistor. At some distance away from the P+ doped regions an N+ doped region is provided. The N-well in between the N+ doped region and base of the transistor forms a parasitic resistor of the ESD protection device. The N+ doped region and the emitter of the transistor are coupled to each other via an electrical connection. The ESD protection device has a limited snapback behaviour and has a well-tunable trigger voltage.

Modeling NMOS snapback characteristic using PSpice

Abstract: Gate-grounded NMOS is often used as ESD protection for circuit design. The ESD behavior of the NMOS transistor is based on the snapback action of its parasitic, lateral NPN BJT. Modeling this behavior of NMOS devices is very important for design of ICs, because there are no standard models, which can be used for describing high current regions in the NMOS snapback characteristic. In this paper an approach of modeling snapback characteristic of NMOS device, intended for use as ESD clamp in IC I/O cells, is proposed. The modeled snapback characteristic is simulated and evaluated using PSPICE.

Impact of snapback behavior on system level ESD performance with single and double stack of bipolar ESD structures

Abstract: ESD system level requirements imply design efforts to achieve fast and robust ESD structures. Several configurations of snapback bipolar ESD structures are tested with TLP measurement from 50ns up to 1us and gun results. Results demonstrate how its robustness depends on the current capability of stacked snapback bipolar structure configuration.

Isolation and protection circuit for a receiver in a wireless communication device

Abstract: A protection circuit protects a receiver from high-energy signals. In one exemplary embodiment, the protection circuit comprises a snapback transistor and a controller. The snapback transistor comprises a gate, a drain connected to an input of the receiver and a source connected to ground. The controller configured to connect the gate to a bias voltage to close the gate in a transmit mode, and to disconnect the gate from the bias voltage to open the gate in a receive mode. The snapback transistor is configured to enter into snapback responsive to a high energy signal at the drain to provide a current path from the drain to the source even when the gate is open and thus protect the receiver.

Effect of embedded-SiGe (eSiGe) on ESD TLP and VFTLP characteristics of diode-triggered silicon controlled rectifiers (DTSCRs)

Abstract: Effect of embedded-SiGe (eSiGe) in anode regions of DTSCRs during TLP and VFTLP testing is investigated. 100ns TLP results of DTSCRs with eSiGe show lower parasitic PNP beta, higher trigger voltage, higher holding voltage and premature snapback failure. Turn-on time measured during VFTLP testing is shown not to be affected by eSiGe due to the breakdown of SCR NW to PW/substrate junction during the initial overshoot.

A novel high speed lateral IGBT with a self-driven second gate

Abstract: A novel lateral IGBT with a second gate on the emitter portion is presented. A PMOS transistor, driven by the proposed device itself, is used to short the PN junction at the emitter while turned off. Low on state voltage and fast turn off speed are obtained without side-effects such as snapback I -V characteristics and difficulties of process complexity. Numerical simulation results show a drop of fall time from 120 to 12 ns and no increase of on state voltage.

A pad ICIM model for EMC immunity simulation

Abstract: Accurate prediction of the response of integrated circuit (IC) to electromagnetic interferences (EMI) is increasingly important. In this paper, a precise integrated circuit immunity model (ICIM) of electrostatic discharge (ESD) protection pads is developed and validated. The model consists of a parasitic RC network model and an ESD snapback model. The parameters of the physically-based parasitic RC network model are extracted from specifically designed structures with ESD pads and validated by S-parameter measurement data. The combined model is able to predict the immunity level more precisely and better support the immunity simulation of circuit under direct power injection (DPI) test.

A short-contacted double anodes IGBT

Abstract: A short contacted double anodes insulated-gate bipolar transistor (DA-IGBT) and its analytic model are proposed. The second anode P 2 is introduced above the metal which suppresses the snapback effectively in its on-state characteristics. Due to its double anodes it shows extraordinary high emission efficiency. As simulation results show, the V F is 1.84v at 100A/cm2, which is decreased by 13% and 23% than those of the Segment Anode IGBT (SA-NPN, 2.1v) and the Short-Anoded IGBT (2.4v), respectively. At off-state, the narrow channel sandwiched between the double anodes can extract the excessive carriers effectively. A shorter turn-off time of 700ns is achieved, which is decreased by 22% and 15% compared to the SA-NPN IGBT (900ns) and the Short-Anoded IGBT (830ns), respectively.

Measurements of the persistent current decay and snapback effect in nb3sn accelerator prototype magnets at fermilab

Abstract: In recent years, Fermilab has been performing an intensive R&D program on Nb3Sn accelerator magnets. This program has included dipole and quadrupole magnets for different programs and projects, including LARP and VLHC. A systematic study of the persistent current decay and snapback effect in the fields of these magnets was executed at the Fermilab Magnet Test Facility. The decay and snapback were measured under a range of conditions including variations of the current ramp parameters and flattop and injection plateau durations. This study has mostly focused on the dynamic behavior of the normal sextupole and dodecapole components in dipole and quadrupole magnets respectively. The paper summarizes the recent measurements and presents a comparison with previously measured NbTi magnets.

Electrostatic discharge protection for class d power amplifiers

Abstract: Electrostatic discharge protection for Class D power amplifiers is disclosed In an exemplary embodiment, an apparatus includes an amplifier having an output transistor coupled to an interface pad, a snapback supply clamp coupled across first and second supplies of the amplifier and configured to provide a clamp voltage across the first and second supplies during ESD event; and a trigger circuit coupled to the output transistor, the trigger circuit configured to detect the clamp voltage and to enable the output transistor to provide a discharge path from the interface pad to the second supply when the clamp voltage is detected

Failsafe ESD protection

Abstract: Among other things, one or more techniques and/or systems for providing failsafe electrostatic discharge (ESD) protection are provided. In one embodiment, ESD protection is provided by connecting a voltage fail safe (VFS) supply voltage to an NWELL circuit interface (e.g., of a PMOS transistor) and connecting PAD to at least one of VFS or the NWELL circuit interface. To this end, circuitry to be protected from ESD (e.g., circuitry operably connected to PAD) is provided with failsafe ESD protection (e.g., such that a non-snapback NMOS device may be utilized to discharge ESD current, where a non-snapback NMOS generally consumes less semiconductor real estate and is less complex to produce as compared to a snapback NMOS), for example. In this manner, failsafe ESD protection is efficiently provided.

Measurements of the persistent current decay and snapback effect in Nb3Sn Fermilab-built accelerator prototype magnets

Abstract: In recent years, Fermilab has been performing an intensive R an D program on Nb{sub 3}Sn accelerator magnets. This program has included dipole and quadrupole magnets for different programs and projects, including LARP and VLHC. A systematic study of the persistent current decay and snapback effect in the fields of these magnets was executed at the Fermilab Magnet Test Facility. The decay and snapback were measured under a range of conditions including variations of the current ramp parameters and flattop and injection plateau durations. This study has mostly focused on the dynamic behavior of the normal sextupole and dodecapole components in dipole and quadrupole magnets respectively. The paper summarizes the recent measurements and presents a comparison with previously measured NbTi magnets.

ESD MOSFET model calibration by differential evolutionary optimization algorithm

Abstract: The aim of this paper is to present the utilization of modern optimization algorithm called Differential Evolution to automatically fit the measured data from test chip to the appropriate electrostatic discharge (ESD) model without the need of manual model-parameters tuning. In contrast with proposed method the traditional approach can be very time and resource consuming. To the best knowledge of the authors, this novel approach has never been previously used. Short introduction to ESD NMOST function and properties are presented along with basic overview of differential evolutionary optimization algorithm. Results of fitting the technology-optimized macro-model of NMOST to the simple piece-wise linear model of MOSFET snapback I-V characteristic will be presented.

High voltage bipolar-based esd protection structure

Abstract: PROBLEM TO BE SOLVED: To provide an area-efficient, high voltage, single polarity ESD protection device.SOLUTION: An ESD protection device 300 includes: a p-type substrate 303; a first p-well 308-1 formed in the substrate and sized to contain n+ and p+ contact regions 310, 312 that are connected to a cathode terminal; a second, separate p-well 308-2 formed in the substrate and sized to contain only a p+ contact region 311 that is connected to an anode terminal; and an electrically floating isolation structure 304, 306, 307-2 formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snapback mode to provide a low impedance path through the structure for discharging an ESD current.

Fast switching and small sized SOI-LTIGBT with shorted trench anode

Abstract: In this paper a novel lateral trench insulated-gate bipolar transistor with shorted trench anode (STA -LTIGBT) on Silicon-on-insulator (SOI) is proposed and discussed. Its main features of the proposed structure are the deep oxide trench in drift region and the trench anode design. Hence the proposed structure could reduce drastically the total chip area not only in the drift region but also in anode region. Numerical simulation results indicate that the proposed STA -LTIGBT structure could suppress the snapback effect commendably. Furthermore, it is shown that the turnoff time of the proposed structure is decreased by 84% compared to that of the conventional LTIGBT, and by 70% compared to that of the deep trench LTIGBT.

Anti-snapback circuitry for metal oxide semiconductor (mos) transistor

Abstract: A circuit for protecting a metal oxide semiconductor (MOS) device is configured to hold down or pull down a voltage at a gate of the protected MOS device during an electrostatic discharge (ESD) event. The circuit includes at least one active device or capacitance-providing element connected to the gate of the protected MOS device, configured to pull down or hold down the voltage at the gate of the protected MOS device when the ESD event occurs.

Method and apparatus for improving triggering uniformity of snapback electrostatic discharge protection devices

Abstract: An electrostatic discharge (ESD) protection circuit includes a first array of transistors, having source and drain doped with a first type of material, arranged in parallel in a first block, and a second array of transistors, having source and drain doped with the first type of material, arranged in parallel in a second block. The ESD protection circuit also includes an active region between the first and second array of transistors doped with a second type of material that is complementary to the first type of material.

Reliability LU Appropriate Designs in an HV nLDMOS

Abstract: In an nLDMOS, both the drain-side and source-side engineering by adding Nad and Pad layers to obtain a weak snapback characteristic are presented in this work. In this paper, we will detailedly discuss the trigger voltage (Vt1) and holding voltage (Vh) distribution of a novel high-voltage (HV) nLDMOS device. It’s a novel method to reduce the Vt1 and to increase the Vh. Therefore, these efforts will be very suitable for the HV applications in power management ICs.