Showing papers on "Wafer published in 1990"

Silicon quantum wire array fabrication by electrochemical and chemical dissolution of wafers

Abstract: Indirect evidence is presented that free‐standing Si quantum wires can be fabricated without the use of epitaxial deposition or lithography. The novel approach uses electrochemical and chemical dissolution steps to define networks of isolated wires out of bulk wafers. Mesoporous Si layers of high porosity exhibit visible (red) photoluminescence at room temperature, observable with the naked eye under <1 mW unfocused (<0.1 W cm−2) green or blue laser line excitation. This is attributed to dramatic two‐dimensional quantum size effects which can produce emission far above the band gap of bulk crystalline Si.

The Evolution of Silicon Wafer Cleaning Technology

Abstract: The purity of wafer surfaces is an essential requisite for the successful fabrication of VLSI and ULSI silicon circuits. Wafer cleaning chemistry has remained essentially unchanged in the past 25 years and is based on hot alkaline and acidic hydrogen peroxide solutions, a process known as "RCA Standard Clean." This is still the primary method used in the industry. What has changed is its implementation with optimized equipment: from simple immersion to centrifugal spraying, megasonic techniques, and enclosed system processing that allow simultaneous removal of both contaminant films and particles. Improvements in wafer drying by use of isopropanol vapor or by "slow‐pull" out of hot deionized water are being investigated. Several alternative cleaning methods are also being tested, including choline solutions, chemical vapor etching, and UV/ozone treatments. The evolution of silicon wafer cleaning processes and technology is traced and reviewed from the 1950s to August 1989.

Gallium arsenide and other compound semiconductors on silicon

Abstract: The physics of the growth mechanisms, characterization of epitaxial structures and device properties of GaAs and other compound semiconductors on Si are reviewed in this paper. The nontrivial problems associated with the heteroepitaxial growth schemes and methods that are generally applied in the growth of lattice mismatched and polar on nonpolar material systems are described in detail. The properties of devices fabricated in GaAs and other compound semiconductors grown on Si substrates are discussed in comparison with those grown on GaAs substrates. The advantages of GaAs and other compound semiconductors on Si, namely, the low cost, superior mechanical strength, and thermal conductivity, increased wafer area, and the possibility of monolithic integration of electronic and optical devices are also discussed.

Generation of femtosecond electromagnetic pulses from semiconductor surfaces

Abstract: We have generated electromagnetic beams from a variety of semiconductors. When a bare semiconductor wafer was illuminated by femtosecond optical pulses, electromagnetic waves radiate from the surface and form collinear diffraction‐limited electromagnetic beams in the inward and outward directions. The amplitude and phase of the radiated field depend on carrier mobility, the strength and polarity of the static internal field at the semiconductor surface.

Low-temperature in-situ dry cleaning process for semiconductor wafers

Abstract: A low-temperature (350° C. to 750° C.) in-situ dry cleaning process for removing native oxide (and other contaminants) from a semiconductor wafer surface, that can be used with either batch or single-wafer semiconductor device manufacturing reactors. A wafer is contacted with a dry cleaning mixture of digermane Ge 2 H 6 and hydrogen gas (51). The digermane-to-hydrogen flow ratio is small enough (usually between 1 ppm to 100 ppm) to ensure effective wafer surface cleaning without any germination deposition. Moreover, the dry cleaning mixture can include a halogen-containing gas (such as HCl or HBr) (52, 54) to enhance removal of metallic contaminants, and/or anhydrous HF gas (53, 54) to further enhance the native oxide removal process. The dry cleaning process can be further activated by introducing some or all of the hydrogen and/or an inert additive gas as a remote plasma. The digermane-based cleaning process of this invention can also be further activated by photo enhancement effects. This dry cleaning process is adaptable as a precleaning step for multiprocessing applications that, during transitions between process steps, reduce thermal cycling (FIGS. 3a-c) by reducing wafer temperature only to an idle temperature (350° C.), and by reducing vacuum cycling via maintaining constant flow rates for carrier gases (FIG. 3a), thereby substantially reducing thermal stress and adsorption of residual impurities, while limiting dopant redistribution.

Formation of a high quality two-dimensional electron gas on cleaved GaAs

Abstract: We have succeeded in fabricating a two-dimensional electron gas (2DEG) on the cleaved (110) edge of a GaAs wafer by molecular beam epitaxy (MBE). A (100) wafer previously prepared by MBE growth is reinstalled in the MBE chamber so that an in situ cleave exposes a fresh (110) GaAs edge for further MBE overgrowth. A sequence of Si-doped AlGaAs layers completes the modulation-doped structure at the cleaved edge. Mobilities as high as 6.1×10^5 cm^2/V s are measured in the 2DEG at the cleaved interface.

Method and apparatus for mechanical planarization and endpoint detection of a semiconductor wafer

Abstract: A method and apparatus for mechanical planarization and endpoint detection of a semiconductor wafer or the like. The apparatus includes a polishing head for rotating the wafer under a controlled pressure against a rotating polishing platen. The polishing head is mounted such that the wafer can be moved across the polishing platen to overhang a peripheral edge of the polishing platen and expose the surface of the wafer. Endpoint detection apparatus in the form of a laser interferometer measuring device is directed at an unpatterned die on the exposed surface of the wafer to detect oxide thickness at that point. The laser light beam is enclosed in a column of liquid to clean the wafer surface at the point of detection and to provide a uniform reference medium for the laser light beam.

Method and apparatus for batch processing a semiconductor wafer

Abstract: A method and apparatus for growing semiconductor quality oxide thermal layers on semiconductor wafers fast enough to be economically feasible as a batch wafer process system. Process speed is insured by high pressure and high temperature. For example, if the pressure is about 10 to 25 atmospheres and at a temperature of 600° C. to 1100° C., approximately 90.0 minutes are required to grow a 5,000 Å oxide layer on about 50 wafers in a steam environment. The system can reach these operating conditions from ambient in approximately 17 minutes and depressurization and cool down require approximately 22 minutes. The apparatus includes a processing chamber to be pressurized with an oxidant, such as high pressure steam or oxygen. The process chamber is contained in a pressure vessel adapted to be pressurized with an inert gas, such as nitrogen, to a high pressure. A pressure control scheme is used to keep the fluid pressure of the process chamber slightly less than the pressure of the fluid pressure vessel. The pressure control permits the use of thin walls of quartz for defining the process chamber.

Method of producing a thin silicon-on-insulator layer

Abstract: 2066193 9105366 PCTABS00004 A process for fabricating thin film silicon wafers using a novel etch stop composed of a silicon-germanium alloy (24) includes properly doping a prime silicon wafer (20) for the desired application, growing a strained Si1-x Gex alloy layer (24) onto seed wafer (20) to serve as an etch stop, growing a silicon layer (26) on the strained alloy layer with a desired thickness to form the active device region, oxidizing the prime wafer (20) and a test wafer (30), bonding the oxide surfaces of the test (30) and prime wafers (20), machining the backside of the prime wafer (20) and selectively etching the same to remove the silicon (20 and 22) removing the strained alloy layer (24) by a non-selective etch, thereby leaving the device region silicon layer (26). In an alternate embodiment, the process includes implanting germanium, tin, or lead ions to form the strained etch stop layer (24).

Wafer fusion: A novel technique for optoelectronic device fabrication and monolithic integration

Abstract: Centimeter‐size single‐crystal InP or GaAs wafers have been fused together entirely, face to face or side by side, after a heat treatment in a graphite/quartz reactor which can press the wafers together through differential thermal expansion. Diodes formed by fusing p‐ and n‐type wafers showed normal current‐voltage characteristics and light emission. Fusion between lattice‐mismatched wafers (i.e., InP and GaAs) has also been demonstrated.

Crystal-Originated Singularities on Si Wafer Surface after SC1 Cleaning

Abstract: It is clarified that a new type of singularity is formed on Si wafer surface by the Standard Cleaning 1 (SC1) of the RCA cleaning process. Such singularities are perceived by laser particle counters as small particles on wafers. It is shown that the singularities correspond to small shallow pits caused by the etching effect of the SC1 cleaning solution. The origin of the pits is presumed to be some kind of defect in the melt-grown crystals.

Method of endpoint detection during chemical/mechanical planarization of semiconductor wafers

Abstract: A method and apparatus for detecting a planar endpoint on a semiconductor wafer during chemical/mechanical planarization of the wafer. The planar endpoint is detected by sensing a change in friction between the wafer and a polishing surface. This change of friction may be produced when, for instance, an oxide coating of the wafer is removed and a harder material is contracted by the polishing surface. In a preferred form of the invention, the change in friction is detected by rotating the wafer and polishing surface with electric motors and measuring current changes on one or both of the motors. This current change can then be used to produce a signal to operate control means for adjusting or stopping the process.

Bistable conditions for low‐temperature silicon epitaxy

Abstract: We report on the role of hydrogen surface passivation in achieving low‐temperature silicon epitaxy by chemical vapor deposition processes. Upon insertion of an HF‐etched silicon wafer into an epitaxial silicon deposition apparatus, residual contamination of the Si surface is negligible. Si 2p core level photoemission spectra demonstrate that the silicon surface is stable in air and free of SiO2 for a time period of minutes. The predominant passivating species is found to be silicon hydride. We demonstrate that hydrogen passivation by HF pretreatment leads to two divergent temperature ranges where epitaxy is successful, those being a low‐temperature range, 425≲T≲650 °C, and a high‐temperature regime, T≳750 °C. Additionally, we employ temperature‐programmed desorption techniques to elucidate the role of hydrogen in the transition to a steady‐state growth process, employing ultrahigh vacuum/chemical vapor deposition as the model system.

Silicon micromechanics: sensors and actuators on a chip

Abstract: The techniques used to fabricate micromechanical structures are described. Bulk micromachining is routinely used to fabricate microstructures with critical dimensions that are precisely determined by the crystal structure of the silicon wafer, by etch-stop layer thicknesses, or by the lithographic masking pattern. Silicon fusion bonding has been used to fabricate micro silicon pressure sensor chips. Surface micromachining, based on depositing and etching structural and sacrificial films, allows the designer to exploit the uniformity with which chemical vapor deposition (CVD) films coat irregular surfaces as well as the patterning fidelity of modern plasma etching processes. Silicon accelerometers, resonant microsensors, motors, and pumps made by these techniques are discussed. Measuring the mechanical properties of silicon, which are important to these applications, is examined. >

Apparatus for testing integrated circuits

Abstract: A membrane probe (10, 12, 14, 16, 58, 144) for testing integrated circuits (56,138) while still on the wafer upon which they are manufactured includes a flexible visually clear and self planarizing membrane (26) having circuit traces (20) and ground shielding planes (14), terminating resistor (152) and active buffer chips (172) formed thereon Probe contact pads (36,38) electroplated on areas of the traces, and connector pads (32) plated on the membrane facilitate rapid detachable connection to a test fixture (50) The probe has a configuration, dimension and structure like that of the wafer itself so that automated pick and place equipment (136, 142) employed for handling the wafers (138) may also be used to handle the probes (144) An unique test fixture (50) is adapted to receive and detachably secure a selected probe to the fixture A metal-on-elastomer annulus (88,104) is employed in the test fixture to make electrical contact between contact pads (32) plated on the back side of the membrane probe and a printed circuit board that is used to route signals to the testing equipment

HF gas etching of wafers in an acid processor

Abstract: Batch processing of semiconductor wafers utilizing a gas phase etching with anhydrous hydrogen fluoride gas flowing between wafers in a wafer carrier. The etching may take place in a bowl with the wafer carrier mounted on a rotor in the closed bowl. The etchant gas may include a small amount of water vapor, along with the anhydrous hydrogen fluoride gas, as may be needed to commence the etching process. The etching may take place with the wafers arranged in a stack in the wafer carrier and extending along or on the rotation axis.

Method of assembling stacks of integrated circuit dies

Abstract: Integrated circuit dies, while still in wafer form, are prepared for stacking without requiring packaging. Holes are made through a wafer having a plurality of integrated circuit dies and are placed between the dies and adjacent the die pads. A layer of insulating material is placed on the wafer and in the outer periphery of the holes. An electrically conductive connection is made between the top of each pad and the inside of the insulating material in an adjacent hole. The insulating layer and the electrically conductive layer can be further extended to the backside of the dies if desired. The dies are separated from each other and can be assembled in a stack and/or surface mounted to a substrate.

Manufacture of semiconductor device

Abstract: PURPOSE:To bring the inner part of a well into the state of low resistance by having high impurity density using the threshold voltage of the transistor in a well region same as that used in the past by a method wherein inverse conductivity type impurity ions are implanted into the region in the vicinity of the surface of the one-conductivity type high density well formed by implanting one-conductivity type high density impurity ions, and an activation heat treatment is performed. CONSTITUTION:After an oxidation treatment of before well formation has been performed, the pattern of the photoresist film 3 to be used for formation of a well is formed by performing a PR process. Phosphorus ions are implanted. Then, the implanted ions are activated, and a heat treatment is performed at 1200 deg.C in a nitrogen atmosphere for the purpose of formation of a high density N-well 4. Subsequently, the N-well region of said high density N-well 4 is subjected counter-ion implantation with boron. Then, boron is ion-implanted on the whole surface of the wafer for the purpose of preventing the generation of a punch through on the N-channel side. Then, the second heat treatment is performed at 1200 deg.C in a nitrogen atmosphere. As a result, the N-well consisting of an N-well 6, the density of which is low in the vicinity of the surface, and a high density N-well 5 of low resistance can be obtained.

Semiconductor dies and wafers and methods for making

Abstract: Disclosed is a method for producing individual semiconductor chips which are singulated from larger wafers, and singulated wafers produced according to the method. Wafers from which the singulated dies are produced include scribe line area through which the wafer is cut by a saw or other method for singulating individual dies. In one aspect of the invention, test pads are provided within the scribe line area for testing of individual dies prior to severing of the wafer. In another aspect of the invention, conventional test circuitry is formed within the scribe line area and utilized in conjunction with text pads for testing operability of individual wafers prior to severing of the wafer into individual chips. Upon test, the scribe lines are severed effectively destroying the sacrificial test pads and circuitry.

Process for metallizing integrated circuits with electrolytically-deposited copper

Abstract: A masked, conformal electrodeposition process for copper metallization of integrated circuits. The process is considerably less complex than other metallization processes utilizing electrodeposition, and provides excellent step coverage for sub-micron contact openings. Full-step coverage has been obtained with the process for contact openings as small as 0.5 microns in diameter. The process begins with the blanket sputter or LPCVD deposition of a thin conductive barrier layer of a material such as titanium nitride, titanium-tungsten or nitrided titanium-tungsten. A photoresist reverse image of the maskwork that normally would be used to etch the metallization pattern on the circuitry is created on the wafer on top of the barrier layer. As an option, the reverse image of the desired metallization pattern may be created by etching a dielectric material layer such as silicon dioxide or silicon nitride, using a photoresist reverse image as a template. The wafer is then transferred to an electrolytic bath, preferably with a pH of 13.5, in which copper is complexed with EDTA molecules. Metallic copper is deposited on the barrier layer where it is not covered by photoresist. At current densities of less than 1 milliamp/cm 2 , the process will automatically fill contact/via openings to a uniform thickness which is independent of the depth of the opening. Following electrodeposition of the metallization layer to the desired thickness, the wafer is removed from the bath, and the photoresist or dielectric material reverse-pattern mask is stripped. At this point, an optional corrosion-resistant metal layer may be galvanically plated on the surface of the copper layer. Finally, portions of the barrier layer that were exposed by removal of the resist are then removed with either a wet or a dry etch.

Apparatus for wafer processing with in situ rinse

Abstract: A wafer processing apparatus including a head defining an etching chamber, the sidewall of the head being slidable along the base so that the sidewall and base will normally define an etch chamber; and the sidewall may be moved upwardly to open a discharge passage for rinsing water, and a deflecting surface for deflecting the rinsing water downwardly and draining the rinsing water from the passage. The housing is separable above the deflector ring to provide access to the wafer for inserting the wafer and replacing it.

Silicon Dioxide Deposition by Atmospheric Pressure and Low‐Temperature CVD Using TEOS and Ozone

Abstract: We report characteristics of the film deposited by an atmospheric pressure and low‐temperature CVD process using TEOS and ozone. Nondoped silicon oxide was deposited on thermally grown oxide, silicon, and aluminum steps. The film surface was very smooth even on aluminum lines and step coverage of the films changed from isotropic to flow shape with ozone concentration increase. This is one of the largest advantages of this CVD technology and is promising for advanced VLSI device fabrication. The film has tensile stress of less than , typically , low enough to fabricate VLSI devices. Film shrinkage was 5% in the film deposited at the higher ozone concentration when annealed at 950°C, which was comparable to that of the conventionally deposited films. The largest thickness without any cracks varied depending on deposition conditions. A thickness of 2 μm without cracks was obtained at 400°C and 0.1 μm/min deposition rate with an ozone concentration of 4.8%. Particle generation was very low and the number of particles of more than 0.3 μm were less than 20 on a 6 in. diam wafer.

Manufacture of semiconductor device

Abstract: PURPOSE:To prevent the surface of a semiconductor wafer from drying, to prevent stain and to early replace chemical on the surface of the wafer with pure water by spraying the pure water to the wafer to be conveyed between a chemical tank and a cleaning tank. CONSTITUTION:Chemical 5 and pure water 7 are filled in a chemical tank 4 and a cleaning tank 6 for processing a wafer, and a nozzle 10 connected to a pure water pipe 11 is provided at the conveying arm 1 of a carrier 2 loaded with the wafer 3. The water 7 in the tank 6 is fed from an inlet 8 to enhance cleaning efficiency, and drained from an outlet 9. The carrier 2 loaded with the wafer 3 is held by the arm 1, and dipped in the tank 4 for a predetermined period of time. Thereafter, it is drawn up, the upper cover 12 of the tank 4 is closed, and the pure water is simultaneously sprayed from the nozzle 10. The carrier 2 is conveyed into the tank 6 as in the state, and dipped for a predetermined period of time.

Method of manufacturing edge connected semiconductor die

Abstract: Die bond locations on a semiconductor die are formed as vertical inserts along the edge of the die. The vertical inserts are isolated from substrate and are exposed by a wafer saw process, in which dice are singulated from a wafer. The configuration offers the advantages of a more efficient layout, allowing the entire top surface of the die to be passivated, a better contact configuration, and more convenient assembly for packaging.

Fabrication of Non‐Underetched Convex Corners in Anisotropic Etching of (100)‐Silicon in Aqueous KOH with Respect to Novel Micromechanic Elements

Abstract: The planes occurring at convex corners during anisotropic etching of (100)‐silicon in aqueous were identified as {411}‐planes, with the help of a specially developed measuring technique. The etching rate of these planes in relation to the rate of the {100}‐planes declines with increasing potassium hydroxide concentration. In contrast, the temperature dependence of this etch rate ratio is negligible in the relevant range between 60°C and 100°C. Based on these results, special structures suited for the compensation of the undercutting in the case of very narrow contours were developed. With the help of these structures it is feasible to realize, for instance, bent V‐grooves or structures with a very low ratio between lateral expansion and etching depth, e.g., a discrete pyramid‐trunk with minimum dimensions on the wafer surface. This offers access to completely new applications, among others spiral channels with double‐sided anisotropic etching for micromechanical heat exchangers; corrugated diaphragms stiffened in two dimensions with low thermal resistance and arbitrary wall thickness; and bellow structures for decoupling mechanical stresses between micromechanical devices and their packaging. Furthermore, this technology paves the way for designing novel types of accelerometers and inclination sensors with external seismic mass.

Refractory semiconductor of boron phosphide

Abstract: The single crystal growth of boron phosphide (BP) by employing the high pressure flux method and chemical vapor deposition (CVD) process is described together with characterization of the prepared BP and its electrical, thermal, semiconducting, and electrochemical properties. BP single crystals prepared by the high pressure flux method contain copper used as the flux, but they are promising for photocathode materials. BP single crystalline wafers prepared by the CVD process using Si wafer substrate contained autodoped silicon with the concentration of 1018−1020 atoms·cm−3, depending on the growth temperature and the substrate plane. The Si atoms which act as acceptors are incorporated at phosphorus sites in BP. The lattice constants determined by the Bond method explain the conduction type of BP. Some electronic transport properties such as donor and acceptor levels and lattice scattering process before and after thermal neutron experiments are clarified. The thermal conduction is limited by three-phonon processes. The formation of defects by thermal neutron irradiation and that of structural disorder by ion-irradiation are mentioned. Schottky diodes consisting of n–BP and Sb or n–BP and Au, which are denoted as n–BP–Sb and –Au, respectively, show excellent characteristics, and their barrier heights are independent of metals and two-thirds of energy bandgap, expected from the surface-state model. Finally, recent results on thermoelectric properties of sintered specimens are mentioned.

Multistep sputtering process for forming aluminum layer over stepped semiconductor wafer

Abstract: A multistep aluminum sputtering process is disclosed wherein aluminum is sputtered onto the surface of a semiconductor wafer and low areas between closely spaced apart raised portions on the wafer, such as closely spaced apart steps, narrow trenches, or small diameter vias, are completely fulled in by the sputtered aluminum. This results in the formation of an aluminum layer which is not thinned out in such low areas, and which has a surface which ranges from substantially planar to a positive slope, such as shown at 24' and 26' in FIG. 2. The first step is carried out by sputtering from about 200 to about 2000 Angstroms of aluminum while the wafer temperature is within a range of from about 50° C. to about 250° C. and the sputtering plasma is at a power of from about 1 to about 16 kilowatts. The power level range is then changed to from about 14 to about 20 kilowatts, a DC or AC bias is applied to the wafer, and aluminum is then sputtered either for an additional time period of about 20 to about 40 seconds or until the wafer temperature reaches 500° C., whichever occurs first, in a second step. Then the back side of the wafer is contacted by a thermally conductive gas to control the wafer temperature while further aluminum is optionally sputtered onto the wafer for an additional 0 to 45 seconds in a third step.

Dry interface thermal chuck temperature control system for semiconductor wafer testing

Abstract: A wafer chuck temperature control system is disclosed for use in a semiconductor wafer testing apparatus. The wafer chuck is divided into a plurality of temperature sensor and cooling element domains corresponding to chip location regions of an overlying undiced wafer being tested. Computer scanning of the sensors determines which domain is the one harboring the heat source (chip under test) and selects the same for connection to a closed loop temperature control feedback servo. Provision also is made for introducing a helium gas interface between the wafer and the chuck by placing annular grooves in the face of the chuck through which the helium flows when the wafer is vacuum-seated against the chuck. A predetermined helium gas flow rate is maintained to preserve vacuum holddown and to optimize the thermal resistance of the wafer-chuck interface.

Sensor for semiconductor device manufacturing process control

Abstract: A fiber-optic sensor device (210) for semiconductor device manufacturing process control measures polycrystalline film thickness as well as surface roughness and spectral emissivity of semiconductor wafer (124). The device (210) comprises a sensor arm (212) and an opto-electronic interface and measurement box (214), for directing coherent laser energy in the direction of semiconductor wafer (124). Opto-electronic interface/measurement unit (214) includes circuitry for measuring the amounts of laser power coherently reflected in the specular direction from the semiconductor wafer (124) surface, scatter reflected from the semiconductor wafer (124) surface, coherently transmitted in the specular direction through the semiconductor wafer (124), and scatter transmitted through the semiconductor wafer (124). The present invention determines the semiconductor wafer (124) surface roughness and spectral emissivity values using the measured optical powers of incident, specular reflected, scatter reflected, specular transmitted, and scatter transmitted beams.

The Evolution of Silicon Wafer Cleaning Technology

Abstract: The purity of wafer surfaces is an essential requisite for the successful fabrication of VLSI and ULSI silicon circuits. Wafer cleaning chemistry has remained essentially unchanged in the past 25 years and is based on hot alkaline and acidic hydrogen peroxide solutions, a process known as "RCA Standard Clean." This is still the primary method used in the industry. What has changed is its implementation with optimized equipment: from simple immersion to centrifugal spraying, megasonic techniques, and enclosed system processing that allow simultaneous removal of both contaminant films and particles. Improvements in wafer drying by use of isopropanol vapor or by "slow‐pull" out of hot deionized water are being investigated. Several alternative cleaning methods are also being tested, including choline solutions, chemical vapor etching, and UV/ozone treatments. The evolution of silicon wafer cleaning processes and technology is traced and reviewed from the 1950s to August 1989.