Showing papers by "Chenming Hu published in 1992"

Electrical characteristics of ferroelectric PZT thin films for DRAM applications

Abstract: Ferroelectric lead zirconate titanate (PZT) films with as much as 2.5 times the storage capacity of the best reported silicon oxide/nitride/oxide (ONO) stacked dielectrics have been fabricated. A 2000-AA film with an effective SiO/sub 2/ thickness of 10 AA is demonstrated. Because of the extremely high dielectric constant ( epsilon /sub r/>or approximately=>1000), even larger storage capacities can be obtained by scaling the ferroelectric film thickness, whereas the thickness of ONO films is limited by direct tunneling through the film. Electrical conduction in the PZT films studied is ohmic at electric fields below 250 kV/cm and follows an exponential field dependence at higher fields, which is shown to be consistent with a simple model for electronic hopping through the film. Leakage current as low as 9*10/sup -8/ A/cm/sup 2/ at 2.5 V for a 4000-AA film is obtained with the addition of La and Fe to compensate for Pb and O vacancies in the film. Further improvement in both leakage current and time-dependent dielectric breakdown characteristics are necessary to ensure reliable DRAM operation. >

Stress-induced current in thin silicon dioxide films

Abstract: Low-field current following Fowler-Nordheim stress of thin gate oxides is studied The conduction mechanism is attributed to trap-assisted tunneling of electrons For oxides thicker than 100 AA, this stress-induced current is observed to decay as traps are filled without significant tunneling out of traps In thinner oxides, steady-state current flows when there is an equilibrium between trap filling and emptying processes This model is observed to be consistent with stress-induced current behavior in a wide range of oxide thicknesses (60 AA to 130 AA) and process technologies >

Ultra-thin silicon dioxide leakage current and scaling limit

Abstract: Modifications are made to Fowler-Nordheim tunneling current analysis to model accurately the measured conduction characteristics of insulator layers thinner than 6 nm. The most significant is direct tunneling for which a closed-form expression is introduced. Polysilicon depletion and electron wave interference are also considered. 4 nm is found to a practical limit for SiO/sub 2/ scaling in VLSI applications due to direct tunneling leakage almost independent of power supply voltage. The convergence of the intrinsic TDDB and gate leakage criteria is established and the possibility that gate leakage will set the ultimate limit to oxide scaling at 4 nm is suggested. >

IC reliability simulation

Abstract: The motivation and challenges of IC reliability simulation are discussed. The reliability simulator BERT is used to illustrate the physical models and approaches used to simulate the hot-electron effect, oxide time-dependent breakdown, electromigration, and bipolar transistor gain degradation. >

Thin oxide damage by plasma etching and ashing processes

Abstract: In the study reported, the plasma Al etching and resist ashing processes caused Fowler-Nordheim current to flow through the oxide. The stress current was collected only through the aluminum surfaces not covered by the photoresist during the plasma processes. The plasma stress current was proportional to the Al pad peripheral length during Al etching and the Al pad area during photoresist stripping. Using the measured stress current, the breakdown voltage distribution of oxides after plasma processes can be predicted accurately. A model of oxide damage due to plasma etching is proposed. >

Interconnect devices for field programmable gate array

Abstract: Field programmable gate arrays (FPGA) use interconnect devices to link logic blocks ranging from single transistors to macrocells. Interconnect devices in use today include MOSFET (SRAM), floating gate memory devices, dielectric and amorphous silicon antifuses. Comparative characteristics of the interconnect devices are discussed. >

Dependence of plasma-induced oxide charging current on Al antenna geometry

Abstract: The dependence of the plasma-induced oxide charging current on Al electrode geometry has been studied. The stress current is collected only through the electrode surfaces not covered by the photoresist during plasma processes and therefore is proportional to the edge length of the electrode during etching and proportional to the electrode area during photoresist ashing. Knowing the measured oxide charging currents, one should be able to predict the impact of these processes on oxide integrity and interface stability for a given antenna geometry more accurately. >

Circuit reliability simulator for interconnect, via, and contact electromigration

Abstract: A model for predicting Al interconnect and intermetallic contact/via electromigration time-to-failure under arbitrary current waveform is incorporated in a circuit electromigration reliability simulator. The simulator can (1) generate layout advisory for width and length of each interconnect, and the number of contacts and vias at each node in a circuit, and (2) estimate the overall circuit electromigration failure rate and/or cumulative percent failure as functions of time, temperature, voltage, frequency, and previous stress (e.g., burn-in). >

Threshold voltage and C-V characteristics of SOI MOSFET's related to Si film thickness variation on SIMOX wafers

Abstract: C-V characteristics of fully depleted SOI MOSFETs have been studied using a technique for measuring silicon-film thickness using a MOSFET. The technique is based on C-V measurements between the gate and source/drain at two different back-gate voltages, and only a large-area transistor is required. Using this technique, SOI film thickness mapping was made on a finished SIMOX wafer and a thickness variation of +or-150 AA was found. This thickness variation causes as much as a 100-mV variation in the device threshold voltage. The silicon-film thickness variation and threshold-voltage variation across a wafer shows a linear correlation dependence for a fully depleted device. C-V measurements of the back-gate device yield the buried-oxide thickness and parasitic capacitances. The effects of GIDL (gate-induced drain leakage) current on C-V characteristics are also discussed. >

A versatile, SOI BiCMOS technology with complementary lateral BJT's

Abstract: A silicon-on-insulator, fully-complementary BiCMOS process has been developed for realizing high-performance circuit operation in the sub-33 V power supply regime Complementary, double-diffused lateral BJTs and fully-overlapped, asymmetrical DDD MOSFETs have been successfully integrated in a 10-mask process by utilizing the process simplifications that are unique to thin-film SOI substrates The BJTs exhibit the highest lateral current gains reported to date, with h/sub fe/=120 and 225 for the NPN and PNP, respectively NPN f/sub t/=45 GHz was achieved, and f/sub t/>20 GHz is possible with an improved layout The MOSFETs demonstrate excellent short-channel behavior down to L/sub eff/=018 mu m, with T/sub ox/=10 nm The p+ gate, SOI PMOS device exhibits superior I/sub dsat/ and g/sub msat/ A record propagation delay of 12 ps/stage at V/sub dd/=5 V and 300 K was obtained for the CMOS ring oscillators fabricated in this technology This demonstrates the performance achievable with a deep-submicron SOI process >

Electromigration in two-level interconnect structures with Al alloy lines and W studs

Abstract: It is demonstrated that electromigration testing needs to be performed in structures that reflect use conditions, such as when there is a flux divergence as provided by the W stud‐Al(Cu) interface rather than in a simple planar structure. The Al(Cu)/W interface has been investigated using both drift velocity and resistometric techniques with pure Al, Al(0.5 wt. % Cu) and Al(2 wt. % Cu) lines on W studs for interlevel connections. It is shown that the mass depletion can be correlated to the resistance change and electromigration failure in line/stud chains. A new effect is demonstrated in that a critical length of Al has to be depleted on Cu before the Al can migrate; when such migration starts the Al catches up with the Cu rich region, leading to slower motion and the production of extrusions which will also cause failures by shorting to adjacent lines.

Simulations of CMOS circuit degradation due to hot-carrier effects

Abstract: By comparing long-term ring-oscillator hot-carrier degradation data and simulation results the authors show that a public-domain circuit simulator, BERT (Berkeley Reliability Tools), can predict CMOS digital circuit speed degradation from transistor DC stress data. Large initial PMOSFET drain current enhancement can result in initial frequency enhancement followed by an initial fast degradation due to the zero crossing effect. The relationship between circuit lifetime and transistor DC stress is examined. >

Gate-induced band-to-band tunneling leakage current in LDD MOSFETs

Abstract: Theoretical and experimental studies are presented to model the gate-induced drain leakage(GIDL) current due to band-to-band tunneling, which is one of the major leakage components in off-state MOSFETs. The model shows a good agreement with the experimental data for more than 7 decades of current magnitudes. Therefore the impact of this tunneling leakage current can be correctly evaluated. Based on this model, the impact of GIDL on low off-state leakage drain engineering and on oxide scaling is investigated. >

Sub‐μm linewidth input coils for low Tc integrated thin‐film dc superconducting quantum interference devices

Abstract: We have, for the first time, demonstrated integrated dc superconducting quantum interference devices (SQUIDs) with input coils of linewidth down to 0.5 μm. The SQUID inductance L consists of a single octagonal washer or two or four such washers configured in parallel. The input coil of inductance Li, which couples to L with a mutual inductance of Mi, consists of fine‐line octagonal spiral(s) fabricated in close proximity to the washer(s). For a two‐washer SQUID with twin 80‐turn, 0.5 μm spirals, Li=2.5 μH, Mi=12.7 nH, L=109 pH, and the coupling constant k2=0.85. This entire device occupies an area of less than 0.2 mm2.

Electromigration performance of electroless plated copper/Pd-silicide metallization

Abstract: The electromigration reliability of Cu interconnects has been studied under DC, pulse-DC, and bipolar current stressing conditions. Electroless plating was used to selectively deposit Cu in oxide trenches by using Pd silicide as a catalytic layer at the bottom of the trenches to initiate copper deposition. The DC and pulse-DC lifetimes of Cu are found to be about two orders of magnitude longer than that of Al-2%Si at 275 degrees C, and about four orders of magnitude longer than that of Al-2%Si when extrapolated to room temperature. On the other hand, Cu AC lifetimes are found to be comparable to the AC lifetimes of Al-2%Si. The pulse-DC lifetime of copper interconnects follows the similar frequency and duty factor dependence as aluminium and the prediction of the vacancy relaxation model. >

Conductive channel in ONO formed by controlled dielectric breakdown

Abstract: Cross-section TEM photos that capture the conductive channel of oxide-nitride-oxide (ONO) films after electric breakdown are discussed. The photos reveal a single crystal or polycrystal channel with a dome-shaped cap depending on the breakdown current. The implications of this structure for electric characteristics is analyzed with a spherical thermal-electric model. When ONO films are used as antifuse on FPGA product, the resistance of the antifuse can be controlled by choosing a sufficiently large programming current level and the resistance remains stable during 1000 h of burn-in at 125 degrees C and 5.75 V. Negligible change in delay time along many different data paths was observed. >

Electrically programmable antifuse having a metal to metal structure

Abstract: A metal-to metal antifuse device is provided in a double layer metal interconnect structure. A lower electrode comprises a first multilayer metal layer interconnect disposed on an insulator. An inter-metal dielectric is disposed on the first metal layer interconnect having an antifuse via. An antifuse material layer is disposed in the antifuse via and having an upper electrode comprising a second multilayer metal layer interconnect.

A new bi-directional PMOSFET hot-carrier degradation model for circuit reliability simulation

Abstract: In this paper, the concept of channel shortening is used to model hot-carrier induced PMOSFET drain current degradation. This new approach models the asymmetric drain current degradation in forward and reverse modes of operation and provides the capability to simulate bi-directional stress. We will present the model, its implementation in BERT (BErkeley Reliability Tools), and simulation results of uni- and bi-directionally stressed circuits. >

Prediction of hot-carrier degradation in digital CMOS VLSI by timing simulation

Abstract: We have adapted an RC time-constant based timing simulator to predict hot-carrier degradation effects in digital CMOS circuits The use of a timing simulator enables a quick characterization of degradation in large circuits The speed-up over SPICE-based simulation can be greater than 3 orders-of-magnitude >

Comparison of electromigration reliability of tungsten and aluminum vias under DC and time-varying current stressing

Abstract: Using Kelvin test structures, the via reliability with respect to electromigration failure of tungsten and aluminum vias under DC, pulse-DC and AC stressing have ben studied The results indicate that although W-plug vias can eliminate the step coverage problem, this metallization system is not ideal because the Al/W contact presents an undesirable flux divergence location for electromigration Al vias are more reliable than W-plug vias with respect to electromigration failure The via lifetimes under bidirectional stressing current were found to be orders of magnitude longer than DC lifetimes under the same stressing current density for both W and al vias The unidirectional 50% duty-factor pulse-DC lifetime was found to be twice the DC lifetime at the low-frequency region ( 10 kHz), in agreement with the vacancy relaxation model >

Internal passivation for suppression of device instabilities induced by backend processes

Abstract: The concept of internal passivation has been introduced as a means of suppressing device degradation due to backend processes. The proposed concept has been demonstrated by tailoring the composition of a PECVD (plasma-enhanced chemical vapor deposition) oxide film to achieve such an internal passivation, resulting in a process with built-in reliability. Specifically, field inversion and hot carrier degradation induced by backend processing have been suppressed. The results have been duplicated on two different commercially available PECVD systems, establishing that neither the problem nor the solution was related to a specific deposition system. >

Simulating hot-carrier effects on circuit performance

Abstract: Hot carriers cause charge trapping in the gate oxide of MOSFETs and generate interface traps at Si/SiO2 interfaces of MOSFETs and bipolar transistors. Models for N-channel and P-channel MOSFETs and for bipolar transistor degradations have been developed and implemented in an IC reliability simulator BERT. Several comparisons between simulation results and measurements are shown. There remain to be answered questions concerning the presence of excess degradation when the stressing signal frequency is high.

Electromigration in Cu/W Structure

Abstract: Mass transport by electromigration in sputtered Cu line segments on a continuous W line has been measured using the drift velocity technique at temperatures from 166 to 396 °C. The Ta/Cu/Ta line segments are patterned by dry etching techniques. Cu mass depletion (voids) at the cathode end and accumulation (hillocks) at the anode were measured as a function of time from scanning electron microscope micrographs. The edge displacement of Cu was found to increase linearly with time. The activation energy for Cu electromigration drift velocity, which relates to the product of effective charge number and diffusivity, Z*D, is found to be 0.6 eV.

Planarized Copper Interconnects by Selective Electroless Plating

Abstract: Electroless deposition of planarized copper in SiO2 trenches has been carried out using Pd/Si plasma immersion ion implantation (PIII) or Pd2Si deposition to form a seed layer at the bottom of trenches. Electrical resistivity of the plated Cu is ≤ 2 μΩ-cm for both types of seeding layers. For the PHI seeding method, we found a threshold Pd dose of 2 ×l014/cm2 is required to initiate Cu plating, and RBS analysis confirms intermixing of Pd, Si, and SiO2 improves the adhesion of the plated Cu to SiO2. Electromigration tests show both void and hillock formation under accelerated current stress testing, with an activation energy of 0.8 eV for interconnect open failure. The DC and pulse-DC median-time-to-failure (MTF) of plated Cu are found to be about two orders of magnitude longer than that of Al-2%Si at 275°C, and about four orders of magnitude longer than that of Al-2%Si when extrapolated to room temperature. Pulsed DC electromigration stressing exhibits a transition from low to high frequency behavior around 900 kHz, indicating a vacancy relaxation time much shorter than that of Al. For bipolar AC stressing, the ratio MTFAC / MTFDC of Cu is much smaller than that of Al-2%Si, indicating a different void recovery mechanism for Cu.

A high speed SOI technology with 12 ps/18 ps gate delay operating at 5 V/1.5 V

Abstract: A high speed Silicon-on-Insulator technology was developed, and a high performance circuit operating at very low power supply voltages was realized. The SOI MOSFETs fabricated on ultra-thin SOI film are fully-depleted and demonstrate excellent short channel behavior. At power supply voltage of V/sub DD/=1.5 V and room temperature, typical propagation delay of 18 ps/stage was obtained for depletion-mode NMOS inverter ring oscillator. The best result shows delay time of 14 ps/stage at V/sub DD/=1.5 V for ring oscillator fabricated on 500 AA SOI film with T/sub ox/=70 AA. This are the best results reported for power supply voltage of 1.5 V at room temperature. >

Plasma-etching induced damage in thin oxide

Abstract: It is pointed out that plasma Al etching and resist ashing processes cause Fowler-Nordheim current to flow through the oxide and that plasma-induced damage can be simulated and modeled as damage produced by constant current electrical stress. The current produced by the plasma process increases with the antenna size of the device structure. C-V measurement is a more sensitive technique for characterizing plasma-etching-induced damage than oxide breakdown. The stress current is collected only through the aluminum surfaces not covered by the photoresist during plasma processes. The plasma stress current is proportional to Al pad peripheral length during Al etching and Al pad area during photoresist stripping. A model of oxide damage due to plasma etching is proposed. >