Showing papers by "Chenming Hu published in 1994"

Hole injection SiO/sub 2/ breakdown model for very low voltage lifetime extrapolation

Abstract: In this paper, we present a model for silicon dioxide breakdown characterization, valid for a thickness range between 25 /spl Aring/ and 130 /spl Aring/, which provides a method for predicting dielectric lifetime for reduced power supply voltages and aggressively scaled oxide thicknesses. This model, based on hole injection from the anode, accurately predicts Q/sub BD/ and t/sub BD/ behavior including a fluence in excess of 10/sup 7/ C/cm/sup 2/ at an oxide voltage of 2.4 V for a 25 /spl Aring/ oxide. Moreover, this model is a refinement of and fully complementary with the well known 1/E model, while offering the ability to predict oxide reliability for low voltages. >

A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation

Abstract: To extend the lower bound of power supply to ultra-low voltages (06 V and below), we propose a dynamic-threshold voltage MOSFET (DTMOS) built on silicon-on-insulator (SOI) The threshold voltage of DTMOS drops as the gate voltage is raised, resulting in a much higher current drive than standard MOSFET at low power supply voltages On the other hand, V/sub t/ is high at V/sub gs/=0, therefore the leakage current is low We provide experimental results and 2-D device and mixed-mode simulations to analyze DTMOS and compare its performance with a standard MOSFET These results verify excellent DC inverter characteristics down to V/sub dd/=02 V, and good ring oscillator performance down to 03 V for DTMOS >

Silicon-on-insulator transistors having improved current characteristics and reduced electrostatic discharge susceptibility

Abstract: An SOI MOSFET having improved electrical characteristics includes a low barrier body contact under the source region, and alternatively under the drain region, to facilitate collection and removal of current carriers generated by impact ionization. Fully-depleted and non-fully-depleted SOI MOSFETs can be integrated on the same chip by providing some transistors with thicker source and drain regions with a recessed channel therebetween and by selective channel dopant implant. Accordingly, digital circuitry and analog circuitry can be combined on one substrate. Improved electrostatic discharge protection is provided by fabricating transistors for the protection circuit directly in the supporting substrate by first removing the silicon thin film and underlying insulation barrier. Alternatively, improved transistors for electrostatic discharge protection can be formed in the silicon film by fabricating the transistor in a plurality of electrically isolated segments, each segment having source and drain regions separated by a channel region with the regions being electrically interconnected with like regions in other segments. Increased ESD current can be realized as compared to the ESD current for a wider unsegmented device.

A dynamic threshold voltage MOSFET (DTMOS) for very low voltage operation

Abstract: A new mode of operation for Silicon-On-Insulator (SOI) MOSFET is experimentally investigated. This mode gives rise to a Dynamic Threshold voltage MOSFET (DTMOS). DTMOS threshold voltage drops as gate voltage is raised, resulting in a much higher current drive than regular MOSFET at low V/sub dd/. On the other hand, V/sub t/ is high at V/sub gs/=0, thus the leakage current is low. Suitability of this device for ultra low voltage operation is demonstrated by ring oscillator performance down to V/sub dd/=0.5 V. >

A capacitorless dram device on silicon-on-insulator substrate

Abstract: A DRAM device has a first semiconductor region (18) of one conductivity on the silicon film of a silicon-on-insulator substrate (22). A second (16) and a third (14) semiconductor region of the opposite conductivity are formed in the first semiconductor region (18). A fourth semiconductor region (12) of the same conductivity type as the first semiconductor region (18) is formed within the second semiconductor region (16) with higher doping concentration. A insulating layer (11) is formed on the semiconductor surface. On top of the insulating layer (11), a gate electrode (10) is formed and is at least partially overlapped with the first (18), the second (16), the third (14), and the fourth (12) semiconductor region. A storage node (24) is formed in the first semiconductor region (18) between the second (16) and the third (14) semiconductor region where the information is stored. The amount of charge stored in the storage node (24) is controlled by a first transistor including the fourth semiconductor region (12), the second semiconductor region (16), the storage node (24), and the gate electrode (10).

Metal‐oxide‐semiconductor field‐effect‐transistor substrate current during Fowler–Nordheim tunneling stress and silicon dioxide reliability

Abstract: The origin of the substrate current of a metal‐oxide‐semiconductor field‐effect transistor when the gate oxide undergoes Fowler–Nordheim stress is investigated. It is also shown that anode hole injection current predicts the breakdown of silicon dioxide between 25 and 130 A and 2.4 and 12 V. While the measured substrate current is entirely due to anode hole injection for oxides thicker than 55 A, tunneling by valence‐band electrons contributes to the substrate current in thinner oxides. Valence‐band electron tunneling current is shown to increase with oxide stressing similar to low‐voltage gate oxide leakage; apparently, both are enhanced by trap‐assisted tunneling. For oxides of thickness between 25 and 130 A, the theory of anode hole injection directly verified for oxides thicker than 55 A is able to model silicon dioxide breakdown accurately.

Reliability of thin SiO2

Abstract: This article reviews reliability phenomena in thin silicon dioxide. We discuss a comprehensive framework for evaluating measured SiO2 breakdown data which enables assurance of built-in oxide reliability for scaled MOS technologies. Promising technological improvements for improving SiO2 reliability are also reviewed. We discuss an integrative view for explaining the many diverse observations about the process of oxide wear-out and failure.

Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation

Abstract: A dynamic threshold voltage IGFET such as a MOSFET is operable at voltages of 0.6 volt or less. The threshold voltage of the transistor is reduced to zero volt or less by interconnecting the gate contact and the device body in which the voltage controlled channel is located. Several efficient connections using through hole plating or polycrystalline silicon gate extension are disclosed. A higher power supply voltage can be used by interconnecting the gate and device body through a smaller MOSFET.

Hot-carrier effects in thin-film fully depleted SOI MOSFET's

Abstract: Previous conflicting reports concerning fully depleted SOI device hot electron reliability may result from overestimation of channel electric field (E/sub m/). Experimental results using SOI MOSFET's with body contacts indicate that E/sub m/ is just a weak function of thin-film SOI thickness (T/sub si/ and that E/sub m/ can be significantly lower than in a bulk device with drain junction depth (X/sub j/) comparable to SOI's T/sub si/. The theoretical correlation between SOI MOSFET's gate current and substrate current are experimentally confirmed. This provides a means (I/sub G/) of studying E/sub m/ in SOI device without body contacts. Thin-film SOI MOSFET's have better prospects for meeting breakdown voltage and hot-electron reliability requirements than previously thought. >

Effects of temperature and defects on breakdown lifetime of thin SiO/sub 2/ at very low voltages

Abstract: This paper investigates the physics of voltage and temperature accelerated breakdown testing of silicon dioxide within the framework of an anode hole injection model which can predict low voltage (3.3 V and below) breakdown lifetime. The field acceleration rate is shown to be independent of temperature, while the reduction of oxide breakdown lifetime at increased temperature is due to the oxide's enhanced susceptibility to damage caused by the holes' transport through the oxide. This paper also investigates defect related breakdown, showing that defects can be mathematically modeled as effective thinning even for aggressively scaled oxides. The effective thickness statistic derived from ramp breakdown or high-field lifetime or charge-to-breakdown tests enables determination of the oxide integrity of a specific oxide technology. For 3.3 V operation, an oxide technology must provide an effective thickness of 44 /spl Aring/; for 2.5 V operation, 34 /spl Aring/. >

SOI (Silicon-on-insulator) for high speed ultra large scale integration

Abstract: Bulk complementary metal-oxide-semiconductor (CMOS) technology scaling can not sustain the historical rate of speed increase. A realistic target for silicon-on-insulator (SOI) delay and power reductions in comparison to bulk technology are 40% and 30%, independent of scaling, mostly through capacitance reduction. Denser isolation allows more compact layout and easy integration of different high speed (E/D NMOS), low power (CMOS), analog (bipolar, grounded-body CMOS) and memory devices. Silicon device speed record (13 ps at 1.5 V, 300 K) has been set with SOI E/D NMOS. Leakage current due to steady state and transient floating-body induced threshold lowering (FITL) is a device issue which deserves more attention.

An electromigration failure model for interconnects under pulsed and bidirectional current stressing

Abstract: An electromigration failure model which can be used to project the electromigration lifetime under pulsed DC and AC current stressing has been reported. The experimental results indicate that different metallization systems (Al-2%Si, Al4%Cu/TiW, and Cu) show similar failure behaviors, which can be explained and predicted by this model. The pulsed DC lifetime is found to be longer than DC lifetime, and the AC lifetime is found to be very much longer. This recognition can provide significant relief to circuit designs involving metals carrying pulsed DC and AC currents, and allow a more aggressive design to improve circuit density and speed. >

Effect of low and high temperature anneal on process-induced damage of gate oxide

Abstract: We have investigated the ability of high and low temperature anneals to repair the gate oxide damage due to simulated electrical stress caused by wafer charging resulting from plasma etching, etc. Even 800/spl deg/C anneal cannot restore the stability in interface trap generation. Even 900/spl deg/C anneal cannot repair the deteriorated charge-to-breakdown and oxide charge trapping. As a small consolation, the ineffectiveness of anneal in repairing the process-induced damage allows us to monitor the damages even at the end of the fabrication process. >

A novel Silicon-On-Insulator (SOI) MOSFET for ultra low voltage operation

Abstract: To extend the lower bound of power supply voltage, we propose a variable threshold voltage MOSFET (VTMOS) built on silicon-on-insulator (SOI). Threshold voltage of VTMOS drops as gate voltage is raised, resulting in a much higher current drive than regular MOSEET, at low Vdd. On the other hand, V/sub t/ is high at V/sub gs/=O, thus the leakage current is low. The SOI devices used in the study were built on SIMOX wafers. A four terminal layout was used to provide separate source, drain, gate, and body contacts.

Interface characterization of fully-depleted SOI MOSFET by a subthreshold I-V method

Abstract: Interface state densities can dramatically affect the performances of MOSFETs by causing threshold voltage shift and mobility degradation. In SOI structures, due to the complex multi-interface nature and small gate area, the interface state characterization still remains a very challenging problem. Conventional C-V method is not suitable for investigating interfaces in SOI MOS devices, mainly because of the large area needed and the high series resistance in thin-film. Several other measurement techniques based on currents rather than capacitance have been proposed. In this work, an evolved technique for characterizing interface state density in fully-depleted SOI MOSFETs is presented. By measuring subthreshold swing of the SOI MOSFETs, the interface state density can be determined. The distribution of both front- and back-interface state densities in the bandgap can be evaluated by applying a rigorous one-dimensional analytical model for FD-SOI MOSFETs operating in the weak inversion regime. In addition, this technique has been applied successfully to the comparison of interface qualities of various SOI wafers and the study of electrical stress effect. The SOI devices used in this study were n-channel and p-channel MOSFETs fabricated with submicron CMOS technology on both SIMOX and Bonded-and-Etchback SOI (BESOI) wafers.

Recessed-channel structure for fabricating ultrathin SOI MOSFET with low series resistance

Abstract: A new recessed-channel SOI (RCSOI) technology has been developed for fabricating ultrathin SOI MOSFET's with low source/drain series resistance. Thin-film fully depleted SOI MOSFET's with channel film thickness of 72 nm have been fabricated with the RCSOI technology. The new structure demonstrated a 70% reduction in source/drain series resistance compared with conventional processes. In the deep-submicron region, more than 80% improvement in saturation drain current and transconductance over conventional devices was achieved using the RCSOI technology. The new technology would also facilitate the use of silicide for further reducing the series resistance. >

Low-voltage CMOS device scaling

Abstract: Discussions of device scaling are often based on simplistic device models. Much more accurate models have become available recently but remain largely unknown to the circuit and design community. This paper highlights some of these models by projecting low-voltage CMOS device trends. >

Effects of temperature and defects on breakdown lifetime of thin SiO/sub 2/ at very low voltages

Abstract: This paper investigates the physics of voltage and temperature accelerated breakdown testing of silicon dioxide within the framework of an anode hole injection model which can predict low voltage (3.3 V and below) breakdown lifetime. The field acceleration rate is shown to be independent of temperature, while the reduction of oxide breakdown lifetime at increased temperature is due to the oxide's enhanced susceptibility to damage caused by the holes' transport through the oxide. This paper also investigates defect related breakdown, showing that defects can be mathematically modeled as effective thinning even for aggressively scaled oxides. The effective thickness statistic derived from ramp breakdown or high-field lifetime or charge-to-breakdown tests enables determination of the oxide integrity of a specific oxide technology. For 3.3 Volt operation, an oxide technology must provide an effective thickness of 44 /spl Aring/; for 2.5 Volt operation, 34 /spl Aring/. >

Comparison of ESD protection capability of SOI and bulk CMOS output buffers

Abstract: ESD protection capability of SOI CMOS output buffers has been studied with human body model (HBM) stresses of both positive and negative polarity. Experimental results show that the ESD discharge current is absorbed by the NMOSFET alone. Unlike bulk technologies where the bi-directional ESD failure voltages are limited by positive polarity stresses, SOI circuits display a more serious reliability problem in handling negative ESD discharge current. Bulk NMOS output buffers fabricated on the substrate of the same SOI wafers, after etching away the buried oxide, have been used to compare the ESD protection capability between bulk and SOI technologies. The ESD voltage sustained by these "bulk" NMOS buffers is about twice the voltage sustained by conventional SOI NMOS buffers. This scheme is proposed as an alternative ESD protection for SOI circuits. The effectiveness of ESD resistant design strategies developed in bulk-substrate technologies when transferred to SOI circuits is also discussed in this paper. >

Hot-carrier-reliability design rules for translating device degradation to CMOS digital circuit degradation

Abstract: Long term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. Initial fast degradation is noted and attributed to the "zero crossing" effect caused by PMOSFET current enhancement. Saturation drain current, measured at V/sub gs/=V/sub ds/=Vdd/2, is a better monitor for CMOS circuit hot-carrier reliability. We present generalized hot-carrier-reliability design rules, lifetime and speed factors, that translate DC device lifetime to CMOS digital circuit lifetime. The design rules can roughly predict CMOS circuit degradation during the initial design and can aid reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors are found to obey 4/ft/sub rise/ and 10/ft/sub fall/, respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor while, for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET lifetime factors are 120 and 300, respectively. >

Electrically programmable antifuse

Abstract: In an antifuse and metal interconnect structure in an integrated circuit a substrate has an insulating layer disposed on an upper surface, a first multilayer metal interconnect layer disposed on the insulating layer, and having a first portion forming a lower antifuse electrode and a second portion forming a lower metal interconnect electrode wherein the first portion includes an upper barrier metal layer. An inter-metal dielectric layer is disposed on the lower antifuse and metal interconnect electrodes wherein the inter-metal dielectric layer includes an antifuse via formed therethrough and communicating with said lower antifuse electrode, and a metal interconnect via former therethrough communicating with the lower metal interconnect electrode, An antifuse material layer is disposed in the antifuse via, and a second multilayer metal interconnect layer is disposed on the antifuse material layer and in the upper metal interconnect electrode via and on the lower metal interconnect electrode.

Comparison of ESD protection capability of SOI and BULK CMOS output buffers

Abstract: ESD protection capability of SOI CMOS output buffers has been studied with human body model (HBM) stresses of both positive and negative polarity. Experimental results show that the ESD discharge current is absorbed by the NMOSFET alone. Unlike bulk technologies where the bi-directional ESD failure voltages are limited by positive polarity stresses, SOI circuits display a more serious reliability problem in handling negative ESD discharge current. Bulk NMOS output buffers fabricated on the substrate of the same SOI wafers, after etching away the buried oxide, have been used to compare the ESD protection capability between bulk and SOI technologies. The ESD voltage sustained by these "bulk" NMOS buffers is about twice the voltage sustained by conventional SOI NMOS buffers. This scheme is proposed as an alternative ESD protection for SOI circuits. The effectiveness of ESD resistant design strategies developed in bulk-substrate technologies when transferred to SOI circuits is also discussed in this paper. >

Optimization of gate oxide N/sub 2/O anneal for CMOSFET's at room and cryogenic temperatures

Abstract: This paper presents a study of the impact of gate-oxide N/sub 2/O anneal on CMOSFET's characteristics, device reliability and inverter speed at 300 K and 85 K. Two oxide thicknesses (60 and 110 /spl Aring/) and five N/sub 2/O anneal conditions (900/spl sim/950/spl deg/C, 5/spl sim/40 min) plus nonnitrided process and channel lengths from 0.2 to 2 /spl mu/m were studied to establish the correlation between the nitrogen concentration at Si/SiO/sub 2/ interface and the relative merits of the resultant devices. We concluded that one simple post-oxidation N/sub 2/O anneal step can increase CMOSFET's lifetime by 4/spl sim/10 times, effectively suppress boron penetration from the P/sup +/ poly-Si gate of P-MOSFET's without sacrificing CMOS inverter speed. We also found that the benefits in terms of the improved interface hardness and charge trapping characteristic still exist at cryogenic temperature. All these improvements are found to be closely correlated to the nitrogen concentration incorporated at the Si/SiO/sub 2/ interface. The optimal N/sub 2/O anneal occurs somewhere at around 2% of nitrogen incorporation at Si/SiO/sub 2/ interface which can be realized by annealing 60/spl sim/110 /spl Aring/ oxides at 950/spl deg/C for 5 min or 900/spl deg/C for 20 min. >

Reliability of thin SiO/sub 2/ at direct-tunneling voltages

Abstract: We investigate the factors that impact thickness scaling of silicon dioxide gate insulators in VLSI technology At low voltages, the direct-tunneling mechanism is shown to result in oxide leakage current orders-of-magnitude higher than predicted by Fowler-Nordheim theory Both intrinsic and defect oxide breakdown reliability is accurately predicted at low voltages using the anode hole injection model The stability of device parameters is investigated to show feasible MOSFET operation in the low voltage, direct-tunneling regime >

Characteristic voltage of programmed metal-to-metal antifuses

Abstract: The characteristic voltage V/sub f/ of different programmed metal-to-metal antifuses was measured and found to be nearly independent of the electrode materials. An electrothermal model, used previously to predict programmed silicon-electrode antifuse resistance, was extended to explain the above phenomenon. The metal-to-metal antifuse resistance vs. the programming current is governed by the Wiedeman-Franz Law. >

Simulating the competing effects of P- and N-MOSFET hot-carrier aging in CMOS circuits

Abstract: A PMOSFET hot-carrier degradation model has been incorporated into the reliability simulator BERT-CAS, enabling prediction of dynamic circuit-level degradation in which both PMOSFET and NMOS-FET degradation play a major role. Comparisons with measured data from CMOS ring oscillator frequency shifts show that full aging simulation by CAS can correctly predict the initial frequency increase due to the PMOSFET current enhancement, and the eventual frequency decrease due to the NMOSFET current degradation. >

Method of fabricating a self-aligned high speed MOSFET device

Abstract: A high speed MOSFET device includes a punchthrough stopper region in the channel of the device formed by high energy ion implantation through the gate electrode and self-aligned therewith. The device has reduced capacitance. A self-aligned recessed channel MOSFET structure includes the punchthrough stopper region to further improve short channel device behavior.

A complete radiation reliability software simulator

Abstract: In this paper we describe a simulator which can be used to study the effects on circuit behavior of two radiation phenomena: single event upset (SEU) and total-dose radiation effects. Using this simulator the user can predict the error rate in large circuits due to single event upset. The error rate model described here uses a well established methodology, but for the first time a different choice is made on picking up the sensitive nodes, enabling a quick prediction even for very complex circuits. The simulator predicts circuit behavior after total-dose irradiation using as inputs: the dose rate and the total dose. Parameter sets that characterize the transistor response to radiation. And the circuit netlist. The total-dose simulator is based on physical models of the changes in the MOSFET caused by radiation. We quantify the degradation of each MOSFET in a circuit with two parameters and determine the change in the MOSFET characteristics-from preirradiation MOSFET data. Using the "irradiated" MOSFET parameters. We can simulate circuit behavior using an ordinary circuit simulator such as SPICE. With this simulator, one can study how resistant a circuit is to changes due to irradiation and design circuits to be functionally radiation "hard" The "double-kink" in the MOSFET subthreshold region due to the parasitic effect of the edge transistors can be simulated and the user is advised when leakage current is unacceptably large. The speed degradation of a ring oscillator was simulated and the results compared with actual measured data. >

Body self bias in fully depleted and non-fully depleted SOI devices

Abstract: One major advantage in SOI processing is the ease of device isolation. By using mesa etching or field oxidation the silicon film can be selectively removed, thereby electrically isolating the bodies of SOI devices from one another. Each body can be individually biased or in most cases, left floating. However there are anomalies associated with a floating body, namely threshold voltage shifting, kink in the current characteristics, and degradation of output resistance in the saturation region. Such anomalies arise because the floating body potential changes with the external biases, which in turn changes the threshold voltage. The amount of body potential shifting is also dependent on the technology and the material qualities. To eliminate these anomalies different schemes have been proposed to bias the body. These schemes add to the process complexity and increase the device area. It is also unclear if such schemes are effective in biasing the body of a fully depleted device, in which case the presence of a quasi-neutral body is lacking. In this paper we have developed a model to predict the body potentials of both Fully Depleted (FD) and Non-Fully Depleted (NE) SOI devices. We found that contrary to general belief the kink anomaly also occurs in FD SOI. However the kink effect diminishes as the film thickness is reduced. For thin silicon film SOI devices, output resistance for floating body long channel SOI devices can be larger than 1 M/spl Omega/-/spl mu/m.