Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

https://users.encs.concordia.ca/~ymzhang/publications/ARC32-2-98Zhang_pp.229-252.pdf

Bibliographical review on reconfigurable fault-tolerant control systems

This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

With advanced computer technology, systems are getting larger to fulfill more complicated tasks: however, they are also becoming less reliable. Consequently, testing is an indispensable part of system design and implementation; yet it has proved to be a formidable task for complex systems. This motivates the study of testing finite stare machines to ensure the correct functioning of systems and to discover aspects of their behavior. A finite state machine contains a finite number of states and produces outputs on state transitions after receiving inputs. Finite state machines are widely used to model systems in diverse areas, including sequential circuits, certain types of programs, and, more recently, communication protocols. In a testing problem we have a machine about which we lack some information; we would like to deduce this information by providing a sequence of inputs to the machine and observing the outputs produced. Because of its practical importance and theoretical interest, the problem of testing finite state machines has been studied in different areas and at various times. The earliest published literature on this topic dates back to the 1950's. Activities in the 1960's mid early 1970's were motivated mainly by automata theory and sequential circuit testing. The area seemed to have mostly died down until a few years ago when the testing problem was resurrected and is now being studied anew due to its applications to conformance testing of communication protocols. While some old problems which had been open for decades were resolved recently, new concepts and more intriguing problems from new applications emerge. We review the fundamental problems in testing finite state machines and techniques for solving these problems, tracing progress in the area from its inception to the present and the stare of the art. In addition, we discuss extensions of finite state machines and some other topics related to testing.

Principles and methods of testing finite state machines-a survey

Ultrathin films of single-walled carbon nanotubes (SWNTs) represent an attractive, emerging class of material, with properties that can approach the exceptional electrical, mechanical, and optical characteristics of individual SWNTs, in a format that, unlike isolated tubes, is readily suitable for scalable integration into devices. These features suggest the potential for realistic applications as conducting or semiconducting layers in diverse types of electronic, optoelectronic and sensor systems. This article reviews recent advances in assembly techniques for forming such films, modeling and experimental work that reveals their collective properties, and engineering aspects of implementation in sensors and in electronic devices and circuits with various levels of complexity. A concluding discussion provides some perspectives on possibilities for future work in fundamental and applied aspects.

http://www.ifc.dicp.ac.cn/library/cailiao/pdf1/11.pdf

Ultrathin Films of Single-Walled Carbon Nanotubes for Electronics and Sensors: A Review of Fundamental and Applied Aspects

Reversible logic design is a well-known paradigm in digital computation. In this paper, quantum-dot cellular automata (QCA) is investigated for testable implementations of reversible logic in array systems. C-testability of a ID array is investigated for multiple cell faults. It has been shown that fault masking is possible in the presence of multiple faults [9]. A technique for achieving C-testability of ID array is introduced by adding lines for controllability and observability. Rules for choosing lines for controllability and observability are proposed. Examples using the QCA reversible logic gates proposed in [9] are presented.

Testing Reversible One-Dimensional QCA Arrays for Multiple F

This paper presents a novel and efficient approach for reliability enhancement at the RT level. The reliability enhancement is performed by utilizing the available resources of a design in their dead intervals. Such resources are used for constructing dynamic TMR structures that can change per clock cycle. In this method all resources participate in constructing TMR structures at least once per a system input to output flow.To evaluate the proposed fault tolerance technique we consider dependability, and area/latency overhead imposed on a circuit by applying our method. In order to evaluate dependability, faults are injected into our test circuits before and after applying our algorithm and fault coverage is measured. Experimental results show that after applying our method, fault coverage is significantly reduced indicating that the reliability of designs is improved.

RT level reliability enhancement by constructing dynamic TMRS

This paper presents the design of a non-volatile register file using cells made of a SRAM and a Programmable Metallization Cell (PMC) The proposed cell is a symmetric 8T2P (8-transistors, 2PMC) design; it utilizes three control lines to ensure the correctness in its operations (ie Write, Read, Store and Restore) Simulation results using HSPICE are provided for the cell as well as the register file array (both one- and two-dimensional schemes) At cell level, it is shown that the off-state resistance has a limited effect on the Read time, because in the proposed circuit the transistor connecting the PMCs to the SRAM is off While having no significant effect on the Store time, the time of the Restore operation depends on the value of the off-state resistance, ie an increase in off-state PMC resistance causes an increase in Restore time Comparison between non-volatile register files utilizing either PMCs, or Phase Change Memories (PCMs) is provided The register file using PMCs has a faster Store and Read times than the PCM-based counterpart; this is mostly caused by the difference in resistance values for these two non-volatile technologies The lower delay involved in these operations confirms that the proposed PMC-based register file offers significant advantages in terms of delay performance

A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File

This paper addresses configurability testing of dynamic FPGAs, i.e. the process to test the state configuration of the FPGA through specific functions which permits one to establish controllability and observability (by read and write operations). Configurability is accomplished in a dynamic FPGA by using a dedicated CPU interface. The CPU interface is characterized by different functional modules (mainly at register level) to permit state access; this is achieved using mapping, masking and addressing functions, and is tested for stuck-at and bridging faults in the bits of the Map and Mask Registers. The proposed approach for configurability testing has been evaluated on the XC6216 FPGA.

Testing the configurability of dynamic FPGAs

This paper presents a novel approach for compressing functional test data in Automatic Test Equipment (ATE). A practical technique is presented for 2 Dimensional (2D) reordering of test data in which additionally to test vector reordering, column reordering is also applied. An ATE based approach to extract the original test vectors from the 2D ordered data is presented. The advantage of the approach is substantiated using the figure of merit of entropy for the 2D ordered test data of ISCAS benchmark circuits.

Fabrizio Lombardi

Papers

Testing Reversible One-Dimensional QCA Arrays for Multiple F

RT level reliability enhancement by constructing dynamic TMRS

A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File

Testing the configurability of dynamic FPGAs

A Novel Methodology for Functional Test Data Compression by ATE