Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

https://users.encs.concordia.ca/~ymzhang/publications/ARC32-2-98Zhang_pp.229-252.pdf

Bibliographical review on reconfigurable fault-tolerant control systems

This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

With advanced computer technology, systems are getting larger to fulfill more complicated tasks: however, they are also becoming less reliable. Consequently, testing is an indispensable part of system design and implementation; yet it has proved to be a formidable task for complex systems. This motivates the study of testing finite stare machines to ensure the correct functioning of systems and to discover aspects of their behavior. A finite state machine contains a finite number of states and produces outputs on state transitions after receiving inputs. Finite state machines are widely used to model systems in diverse areas, including sequential circuits, certain types of programs, and, more recently, communication protocols. In a testing problem we have a machine about which we lack some information; we would like to deduce this information by providing a sequence of inputs to the machine and observing the outputs produced. Because of its practical importance and theoretical interest, the problem of testing finite state machines has been studied in different areas and at various times. The earliest published literature on this topic dates back to the 1950's. Activities in the 1960's mid early 1970's were motivated mainly by automata theory and sequential circuit testing. The area seemed to have mostly died down until a few years ago when the testing problem was resurrected and is now being studied anew due to its applications to conformance testing of communication protocols. While some old problems which had been open for decades were resolved recently, new concepts and more intriguing problems from new applications emerge. We review the fundamental problems in testing finite state machines and techniques for solving these problems, tracing progress in the area from its inception to the present and the stare of the art. In addition, we discuss extensions of finite state machines and some other topics related to testing.

Principles and methods of testing finite state machines-a survey

Ultrathin films of single-walled carbon nanotubes (SWNTs) represent an attractive, emerging class of material, with properties that can approach the exceptional electrical, mechanical, and optical characteristics of individual SWNTs, in a format that, unlike isolated tubes, is readily suitable for scalable integration into devices. These features suggest the potential for realistic applications as conducting or semiconducting layers in diverse types of electronic, optoelectronic and sensor systems. This article reviews recent advances in assembly techniques for forming such films, modeling and experimental work that reveals their collective properties, and engineering aspects of implementation in sensors and in electronic devices and circuits with various levels of complexity. A concluding discussion provides some perspectives on possibilities for future work in fundamental and applied aspects.

http://www.ifc.dicp.ac.cn/library/cailiao/pdf1/11.pdf

Ultrathin Films of Single-Walled Carbon Nanotubes for Electronics and Sensors: A Review of Fundamental and Applied Aspects

This paper presents a novel HSPICE circuit model for designing and simulating a Single-Electron (SE) turnstile, as applicable at the nanometric feature sizes. The proposed SE model consists of two nearly similar parts whose operation is independent of each other; this disjoint feature permits to accurately model the sequential transfer of electrons through the turnstile in the storage node (modeled on a voltage level basis). It therefore avoids the transient (current-based) nature of a previous model. The model has been simulated and results show that it can correctly operate at 32 nm with excellent stability in its operation. Extensive simulation results are presented to substantiate the advantages of using the proposed model with respect to changes in the circuit model parameter.

Modeling a single electron turnstile in HSPICE

This paper presents two circuits for implementing the restore operation of a non-volatile (NV) memory cell in which data from a programmable metallization cell (PMC) can be copied (restored) into a static random access memory (SRAM). In the first proposed design, a transmission gate is added to each row of cells of the memory array in which a concurrent error detection (CED) circuit is also present. When a mismatch between the data stored in the SRAM and the PMC is detected, the restore operation starts for a single cell. For the second proposed design, a tri-state inverter is added to control the restore operation. This design requires a larger circuit complexity compared to the first design, but performance is substantially improved; moreover, all cells of a memory array can be simultaneously restored, thus suitable for restarting with power-on. A comparison of these designs with a previous scheme is also pursued; it is shown that the proposed designs improve performance.

Designs of PMC-based non-volatile memory circuits for data restoring

This paper deals with a novel graph model to represent tile sets for DNA self-assembly in forward growth under aTAM. This model is based on a tile attachment and captures the features of the so-called corner attachment by considering the binding of the bonds between a tile and the current error-free aggregate. An analysis of this process and its implications on tile sets (such as composition and decomposition) are pursued with respect to the properties of the graph model.

A Graph Model for Tile Sets in DNA Self-Assembly

This paper presents analytical models for evaluating intermediate tests for yield enhancement and quality assurance of systems manufactured using fault-tolerant multichip modules (MCM's) for massively parallel computing (MPC). In the proposed approaches, we employ both a novel Markov model and a so-called working-test-set to compute the yield. Unlike a previous method which utilizes a binomial distribution, our scheme can employ intermediate tests to meet MCM quality requirements effectively. Several strategies for appropriately testing fault-tolerant MCM's have been proposed, but little analytical evaluation has been performed. In this paper, it is shown that an efficient test strategy with a modest level of redundancy may exist to achieve virtually 100% first-pass MCM yield for a particular system. We note that a yield-analysis model employing the LRTWS (Least Recently Tested in WS) test strategy proposed in this paper may provide a very good figure of merit due to its cost, delivery, number of tests and reliability benefits for current technology. Extensive parametric results for the analysis are provided to show that our approach can be applied to calculate the overall yield for fault-tolerant MCM's more accurately and efficiently, thereby improving upon the reliability and quality of the entire system. >

http://ieeexplore.ieee.org/iel4/96/9089/00404102.pdf

Modeling intermediate tests for fault-tolerant multichip module systems

Processing at the nanometric scales presents unique challenges that may require new computational paradigms such as approximate computing. In this paper a novel approach to memory protection using an unequal protection code (UEP) is proposed; this approach is in synergy with approximate (or inexact) computing. Multi-level burst error correcting UEP codes are analyzed. These codes improve over previously presented two-level burst error correcting UEP codes, because they utilize different conditions and criteria in the code partitions and decoder construction. An analysis by which multiple partitions can be selected to reduce the expected error magnitude, is provided. The area and power consumption of the parallel decoders closely depend on the desired code function. Simulation shows that the area and power consumption of the parallel error pattern generator are proportional to the partition length; the gate depth however is not strongly related to the partition length. The results of this manuscript confirm that the proposed multi-level burst error correcting UEP codes reduce the hardware overhead with no significant degradation in storage protection as potential storage application for approximate computing systems.

Fabrizio Lombardi

Papers

Modeling a single electron turnstile in HSPICE

Designs of PMC-based non-volatile memory circuits for data restoring

A Graph Model for Tile Sets in DNA Self-Assembly

Modeling intermediate tests for fault-tolerant multichip module systems

Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems