F
Fabrizio Lombardi
Researcher at Northeastern University
Publications - 677
Citations - 12743
Fabrizio Lombardi is an academic researcher from Northeastern University. The author has contributed to research in topics: Fault detection and isolation & Redundancy (engineering). The author has an hindex of 51, co-authored 639 publications receiving 10357 citations. Previous affiliations of Fabrizio Lombardi include Helsinki University of Technology & Fudan University.
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Proceedings ArticleDOI
Design of majority logic based approximate arithmetic circuits
TL;DR: This paper proposes designs of approximate arithmetic units which are specifically designed for use in majority logic based technologies, which have the potential to further cut power consumption.
Journal ArticleDOI
Security in Approximate Computing and Approximate Computing for Security: Challenges and Opportunities
TL;DR: A classification of the state-of-the-art works in this research field, including threat models in approximate computing and promising security approaches using approximate computing are provided.
Journal ArticleDOI
Majority Logic Formulations for Parallel Adder Designs at Reduced Delay and Circuit Complexity
TL;DR: Two new majority gate-based recursive techniques are proposed that result in the calculation of the output carry of an multi-bit adder with only a majority gate delay of $\boldsymbol{n}$, which leads to a reduction of 40percent in delay and 30percent in circuit complexity for multi- bit addition in comparison to the best existing designs found in the technical literature.
Proceedings ArticleDOI
A XOR-tree based technique for constant testability of configurable FPGAs
TL;DR: It is shown that the proposed testing arrangement requires a number of tests independent of the number of CLBs in the FPGA (i.e. C-testability is accomplished) and compatibility for a CAD implementation is also accomplished.
Journal ArticleDOI
A Novel Heuristic Method for Application-Dependent Testing of a SRAM-Based FPGA Interconnect
TL;DR: This paper presents a new method for generating configurations for application-dependent testing of a SRAM-based FPGA interconnect that connects an activating input to multiple nets, thus generating activating test vectors for detecting stuck-at, open, and bridging faults.