Probability Distributions.- Linear Models for Regression.- Linear Models for Classification.- Neural Networks.- Kernel Methods.- Sparse Kernel Machines.- Graphical Models.- Mixture Models and EM.- Approximate Inference.- Sampling Methods.- Continuous Latent Variables.- Sequential Data.- Combining Models.

Pattern Recognition and Machine Learning

https://users.encs.concordia.ca/~ymzhang/publications/ARC32-2-98Zhang_pp.229-252.pdf

Bibliographical review on reconfigurable fault-tolerant control systems

This ebook is the first authorized digital version of Kernighan and Ritchie's 1988 classic, The C Programming Language (2nd Ed.). One of the best-selling programming books published in the last fifty years, "K&R" has been called everything from the "bible" to "a landmark in computer science" and it has influenced generations of programmers. Available now for all leading ebook platforms, this concise and beautifully written text is a "must-have" reference for every serious programmers digital library.

As modestly described by the authors in the Preface to the First Edition, this "is not an introductory programming manual; it assumes some familiarity with basic programming concepts like variables, assignment statements, loops, and functions. Nonetheless, a novice programmer should be able to read along and pick up the language, although access to a more knowledgeable colleague will help."

The C programming language

With advanced computer technology, systems are getting larger to fulfill more complicated tasks: however, they are also becoming less reliable. Consequently, testing is an indispensable part of system design and implementation; yet it has proved to be a formidable task for complex systems. This motivates the study of testing finite stare machines to ensure the correct functioning of systems and to discover aspects of their behavior. A finite state machine contains a finite number of states and produces outputs on state transitions after receiving inputs. Finite state machines are widely used to model systems in diverse areas, including sequential circuits, certain types of programs, and, more recently, communication protocols. In a testing problem we have a machine about which we lack some information; we would like to deduce this information by providing a sequence of inputs to the machine and observing the outputs produced. Because of its practical importance and theoretical interest, the problem of testing finite state machines has been studied in different areas and at various times. The earliest published literature on this topic dates back to the 1950's. Activities in the 1960's mid early 1970's were motivated mainly by automata theory and sequential circuit testing. The area seemed to have mostly died down until a few years ago when the testing problem was resurrected and is now being studied anew due to its applications to conformance testing of communication protocols. While some old problems which had been open for decades were resolved recently, new concepts and more intriguing problems from new applications emerge. We review the fundamental problems in testing finite state machines and techniques for solving these problems, tracing progress in the area from its inception to the present and the stare of the art. In addition, we discuss extensions of finite state machines and some other topics related to testing.

Principles and methods of testing finite state machines-a survey

Ultrathin films of single-walled carbon nanotubes (SWNTs) represent an attractive, emerging class of material, with properties that can approach the exceptional electrical, mechanical, and optical characteristics of individual SWNTs, in a format that, unlike isolated tubes, is readily suitable for scalable integration into devices. These features suggest the potential for realistic applications as conducting or semiconducting layers in diverse types of electronic, optoelectronic and sensor systems. This article reviews recent advances in assembly techniques for forming such films, modeling and experimental work that reveals their collective properties, and engineering aspects of implementation in sensors and in electronic devices and circuits with various levels of complexity. A concluding discussion provides some perspectives on possibilities for future work in fundamental and applied aspects.

http://www.ifc.dicp.ac.cn/library/cailiao/pdf1/11.pdf

Ultrathin Films of Single-Walled Carbon Nanotubes for Electronics and Sensors: A Review of Fundamental and Applied Aspects

A multiplier has a significant impact on the speed and power dissipation of an arithmetic processor. Precise results are not always required in many algorithms, such as those for classification and recognition in data processing. Moreover, many errors do not make an obvious difference in applications such as image processing due to the perceptual limitations of human beings. Error-tolerant algorithms and applications have promoted the development of approximate multipliers to tradeoff accuracy for speed, implementation area and/or power efficiency. This paper briefly reviews the current designs of approximate multipliers and provides a comparative evaluation of their error and circuit characteristics. Image sharpening is performed using the considered approximate multipliers to assess their performance in such applications.

A comparative evaluation of approximate multipliers

As the physical gate length of current devices is reduced to below 65 nm, effects (such as large parametric variations and increase in leakage current) have caused the I-V characteristics to be substantially depart from those commonly associated with traditional MOSFETs, thus impeding the efficient development and manufacturing of devices at deep submicro/nano scales. Carbon Nanotube Field Effect Transistors (CNFETs) have received widespread attention, as one of the promising technologies for replacing MOSFETs at the end of the Technology Roadmap. This paper presents a detailed simulation-based assessment of circuit performance of this technology and compares it to conventional MOSFETs; the designs of different logic gates and the full adder circuit are simulated under the same minimum gate length and different operational conditions. It is shown that the power-delay product (PDP) and the leakage power for the CNFET based gates are lower than the MOSFET based logic gates by 100 to 150 times, respectively. The CNFET based logic gates demonstrate good functionality even at a 0.3 V power supply (while MOSFET based gates fail at 0.5 V).

Performance evaluation of CNFET-based logic gates

This efficient approximation model for the drain-source current in a CNFET is analytic, its execution is fast, and it is suitable for simulating circuits consisting of many CNFET devices in a CAD environment. Evaluation results show that the model encounters a very modest normalized RMS error for diameter, Fermi level, and bias variations, while significantly improving simulation performance.

Device Model for Ballistic CNFETs Using the First Conducting Band

Stochastic computation has recently been proposed for implementing artificial neural networks with reduced hardware and power consumption, but at a decreased accuracy and processing speed. Most existing implementations are based on pre-training such that the weights are predetermined for neurons at different layers, thus these implementations lack the ability to update the values of the network parameters. In this paper, a stochastic computational multi-layer perceptron (SC-MLP) is proposed by implementing the backward propagation algorithm for updating the layer weights. Using extended stochastic logic (ESL), a reconfigurable stochastic computational activation unit (SCAU) is designed to implement different types of activation functions such as the $tanh$ and the rectifier function. A triple modular redundancy (TMR) technique is employed for reducing the random fluctuations in stochastic computation. A probability estimator (PE) and a divider based on the TMR and a binary search algorithm are further proposed with progressive precision for reducing the required stochastic sequence length. Therefore, the latency and energy consumption of the SC-MLP are significantly reduced. The simulation results show that the proposed design is capable of implementing both the training and inference processes. For the classification of nonlinearly separable patterns, at a slight loss of accuracy by 1.32-1.34 percent, the proposed design requires only 28.5-30.1 percent of the area and 18.9-23.9 percent of the energy consumption incurred by a design using floating point arithmetic. Compared to a fixed-point implementation, the SC-MLP consumes a smaller area (40.7-45.5 percent) and a lower energy consumption (38.0-51.0 percent) with a similar processing speed and a slight drop of accuracy by 0.15-0.33 percent. The area and the energy consumption of the proposed design is from 80.7-87.1 percent and from 71.9-93.1 percent, respectively, of a binarized neural network (BNN), with a similar accuracy.

A Stochastic Computational Multi-Layer Perceptron with Backward Propagation

Deep sub-micrometer/nano CMOS circuits are more sensitive to externally induced radiation phenomena that are likely to cause the occurrence of so-called soft errors. Therefore, the tolerance of the circuit to the soft errors is a strict requirement in nanoscale circuit designs. Since the traditional error tolerant methods result in significant cost penalties in terms of power, area, and performance, the development of low-cost hardened designs for storage cells (such as latches and memories) is of increasing importance. This paper proposes three new hardened designs for CMOS latches at 32 nm feature size; these circuits are Schmitt trigger based, while the third one utilizes a cascode configuration in the feedback loop. The Cascode ST latch has 112% higher critical charge than the conventional reference latch with only 10% area increase. A novel design metric (QPAR) for latches is introduced to assess the overall design effectiveness such as area, performance, power, and soft error tolerance. The novel metric (QPAR) shows the proposed cascode ST latch achieves up to 36% improvement in terms of QPAR compared with the existing hardening designs. Monte Carlo analysis has confirmed the robustness of the proposed hardened latches to process, voltage, and temperature (PVT) variations.

Fabrizio Lombardi

Papers

A comparative evaluation of approximate multipliers

Performance evaluation of CNFET-based logic gates

Device Model for Ballistic CNFETs Using the First Conducting Band

A Stochastic Computational Multi-Layer Perceptron with Backward Propagation

Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS