There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

In this paper, recent progress of binary metal-oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed.

Metal–Oxide RRAM

The tunnel field-effect transistor (TFET) is one of the prime steep-slope device candidates to be employed in future ultra-low power logic applications [1], [2], and can achieve sub-60 mV/dec subthreshold swings (SS) using quantum mechanical (QM) band-to-band tunneling (BTBT). One of the main challenges for TFETs is obtaining a sufficiently high drive-current $\mathrm{I}_{\mathrm{ON}}$ [1]. The $\mathrm{I}_{\mathrm{ON}}$ can be enhanced by introducing a highly-counter-doped pocket at the tunnel junction [3], [4]. However, it is well known that high doping concentrations introduce band-tails states in the bandgap [5]. First assessments on band-tails in TFETs, linked to diode measurements, have been made [6]–[8]. However, it is unknown whether the band-tails-induced tunneling contributions limit the performance of optimized pocketed TFETs. In this work, we investigate the impact of band-tails on the SS of p-n-i-n $\mathrm{In}_{0.53}\mathrm{Ga}_{0.47}\mathrm{As}$ and InAs TFETs for different pocket thicknesses and doping concentrations in the source and pocket, while using band-tails density-of-states (DOS) obtained from successful diode calibrations [8].

Impact of calibrated band-tails on the subthreshold swing of pocketed TFETs

In this paper we describe a structure designed and fabricated for the purpose of locating successive SBD's in 2D. It is shown that the original BD location method can be readily extended to 2D, for both accumulation (Degraeve et al., 2001) and inversion (Crupi et al., 2005). It is concluded that the locations of two successive SBD's can be readily distinguished and that subsequent SBD events do not appear to be correlated within the analysis of this work. Limitations in downscaling the structure are also discussed.

Proof-of-Concept Structure for Investigation of Successive Soft Gate Oxide Breakdowns in Two Dimensions

Silicon photonics interposers enable low power, high bandwidth signal transfer between CMOS chips. Optical wave guides transfer the optical signal that carries the information. Optical modulator and detectors realize the optical to electrical signal transfer and vice versa. These components could be facing ESD stress during assembly. This work presents an in-depth study the self-protecting capabilities of these components and provides an ESD protection solution to increase the ESD robustness.

Guido Groeseneken

Papers

Impact of calibrated band-tails on the subthreshold swing of pocketed TFETs

Proof-of-Concept Structure for Investigation of Successive Soft Gate Oxide Breakdowns in Two Dimensions

Bidirectional NPN ESD protection in silicon photonics technology

Invited) Reliability of SiGe Channel MOS

System-level ESD protection of high-voltage tolerant IC pins-A case study