There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

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Fundamentals of Modern VLSI Devices

Power dissipation is a fundamental problem for nanoelectronic circuits. Scaling the supply voltage reduces the energy needed for switching, but the field-effect transistors (FETs) in today's integrated circuits require at least 60 mV of gate voltage to increase the current by one order of magnitude at room temperature. Tunnel FETs avoid this limit by using quantum-mechanical band-to-band tunnelling, rather than thermal injection, to inject charge carriers into the device channel. Tunnel FETs based on ultrathin semiconducting films or nanowires could achieve a 100-fold power reduction over complementary metal-oxide-semiconductor (CMOS) transistors, so integrating tunnel FETs with CMOS technology could improve low-power integrated circuits.

Tunnel field-effect transistors as energy-efficient electronic switches

In this paper, recent progress of binary metal-oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal-oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed.

Metal–Oxide RRAM

A comprehensive analysis of the NBTI reliability of SiGe channel pMOSFETs is reported in this chapter. First the impact of individual gate stack parameters on the device reliability is discussed. The experimental learning is then combined to propose a reliability-oriented gate stack optimization, which is shown to enable ultrathin EOT devices with sufficient reliability, i.e., 10 years of continuous operation at nominal V DD. The demonstrated results are shown to be process- and architecture-independent and as such, directly transferable to other device technologies such as pure Ge channel and wrapped SiGe channel finFETs. A detailed experimental analysis of the NBTI kinetics on SiGe channel devices is proposed and compared with Si channel reference devices. The interplay between NBTI and Body Biasing on Si and SiGe devices is discussed, showing that it can yield further benefit for the novel technology. A model capable of explaining all the experimental observations is proposed. Finally, some considerations about the correlation of device performance and reliability are made.

Negative Bias Temperature Instability in (Si)Ge pMOSFETs

Electrical interface characterization of non-Si Based MOSFETs: challenges and solutions

I. Introduction The growing demand for power efficient devices has accelerated the research into the use of the tunnel field-effect transistor (TFET) in future ultra-low power applications because of its promising potential for sub-60 mV/dec subthreshold swing achieved through quantum mechanical band-to-band tunneling (BTBT) [1]-[3]. Unfortunately, a significant gap between theoretical predictions and experiments remains to be bridged [2]. Considerable efforts are being made to develop models for some of the main causes of suboptimal TFET performance such as trap-assisted tunneling (TAT) [4], [5], phonon-assisted tunneling (PAT) [6], and Auger generated leakage currents [7]. However, aside from qualitative analyses [8] and purely predictive work on the device impact of tunneling transitions involving high-doping induced band-tails states in InSb nanowire TFETs [9] and 2D-TFETs [10], no attempts have been made to calibrate these contributions. This work aims to fill this gap by developing and calibrating an approximate ballistic semi-classical (SC) model for high-doping induced band-tails using the experimental I-V data of In0.53Ga0.47As p-i-n Esaki diodes [11]. The hypothesis is posited that the mismatch between measurement and simulation in the negative differential resistance regime (see Fig. 1), which cannot be explained by SC TAT models, is caused by ballistic band-tails tunneling. The calibration thus gives an upper limit to the band-tails current. Lastly, the impact of band-tails on the performance of a p-n-i-n TFET is investigated.

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Calibration of the high-doping induced ballistic band-tails tunneling current with In 0.53 Ga 0.47 As Esaki diodes

Charging Instability in n-Channel MOS-FETs with SiO2/HfO2 Gate Dielectric

The above-named article [ibid., vol. 60, no. 7, pp. 2128?-134, Jul. 2013] contains an error in the legend of Fig. 11. The correct version is provided.

Guido Groeseneken

Papers

Negative Bias Temperature Instability in (Si)Ge pMOSFETs

Electrical interface characterization of non-Si Based MOSFETs: challenges and solutions

Calibration of the high-doping induced ballistic band-tails tunneling current with In 0.53 Ga 0.47 As Esaki diodes

Charging Instability in n-Channel MOS-FETs with SiO2/HfO2 Gate Dielectric

Corrections to “Quantum Mechanical Performance Predictions of p-n-i-n Versus Pocketed Line Tunnel Field-Effect Transistors” [Jul 13 2128-2134]