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Guido Groeseneken

Researcher at Katholieke Universiteit Leuven

Publications -  1085
Citations -  29081

Guido Groeseneken is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Gate oxide & CMOS. The author has an hindex of 73, co-authored 1074 publications receiving 26977 citations. Previous affiliations of Guido Groeseneken include Siemens & Liverpool John Moores University.

Papers
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Proceedings ArticleDOI

Implications of progressive wear-out for lifetime extrapolation of ultra-thin (EOT /spl sim/ 1 nm) SiON films

TL;DR: In this article, a semi-empirical model for progressive breakdown wearout is constructed and a corrected methodology for reliability extrapolation for ultrathin oxides is proposed, which is greatly hindered by the inability to detect the actual first breakdown.
Journal ArticleDOI

Influence of tester, test method, and device type on CDM ESD testing

TL;DR: In this paper, the authors compared the characteristic waveforms defined by the EOS/ESD CDM ESD draft standard (DS5.3-1993), and some major problems related to the specification of socketed CDM testers are discussed.
Journal ArticleDOI

Carbon nanotube–carbon nanotube contacts as an alternative towards low resistance horizontal interconnects

TL;DR: In this article, the authors proposed to use carbon nanotube (CNT)-CNT contacts instead of CNT-metal contacts as a route towards low-resistance CNT horizontal interconnects.
Proceedings ArticleDOI

T-diodes - a novel plug-and-play wideband RF circuit ESD protection methodology

TL;DR: In this article, a plug-and-play ESD protection methodology for wideband RF applications is proposed, which utilizes an integrated transformer together with classical EDS protection elements for a wideband LNA in 0.18 mum CMOS.
Journal ArticleDOI

Abrupt breakdown in dielectric/metal gate stacks: a potential reliability limitation?

TL;DR: In this paper, the authors demonstrate that the large abrupt current increase (/spl Delta/I) as compared to poly-Si is not likely due to process issues, but is an intrinsic property of the dielectric/metal gate stack.