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Guido Groeseneken
Researcher at Katholieke Universiteit Leuven
Publications - 1085
Citations - 29081
Guido Groeseneken is an academic researcher from Katholieke Universiteit Leuven. The author has contributed to research in topics: Gate oxide & CMOS. The author has an hindex of 73, co-authored 1074 publications receiving 26977 citations. Previous affiliations of Guido Groeseneken include Siemens & Liverpool John Moores University.
Papers
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Proceedings Article
Test circuits for fast and reliable assessment of CDM robustness of I/O stages
Wolfgang Stadler,Kai Esmark,Koen Reynders,Mahmud Zubeidat,M. Graf,Wolfgang Wilkening,J. Willemen,N. Qu,S. Mettler,M. Etherton,D. Nuernbergk,Heinrich Wolf,H. Gieser,W. Soppa,V. De Heyn,M.I. Natarajan,Guido Groeseneken,E. Morena,Roberto Stella,Antonio Andreini,Martin Litzenberger,Dionyz Pogany,Erich Gornik,C. Foss,A. Konrad,M. Frank +25 more
TL;DR: This paper introduces a method on the basis of specialized CDM test structures including protection elements and sensitive monitor elements that mimic typical CDM-sensitive circuits found by physical failure analysis over the years.
Journal ArticleDOI
Full-zone spectral envelope function formalism for the optimization of line and point tunnel field-effect transistors
Devin Verreck,Anne S. Verhulst,Maarten L. Van de Put,Maarten L. Van de Put,Bart Sorée,Bart Sorée,Wim Magnus,Wim Magnus,Anda Mocuta,Nadine Collaert,Aaron Thean,Guido Groeseneken +11 more
TL;DR: In this paper, a full-zone 15-band quantum mechanical solver based on the envelope function formalism and employing a spectral method to reduce computational complexity and handle spurious solutions is presented.
Proceedings ArticleDOI
Advanced ESD power clamp design for SOI FinFET CMOS technology
Steven Thijs,David Trémouilles,Dimitri Linten,Natarajan Mahadeva Iyer,Alessio Griffoni,Guido Groeseneken +5 more
TL;DR: In this paper, two novel ESD power clamp design techniques for SOI FinFET CMOS technology are reported, which reduce the required area for a given ESD robustness and at the same time reduce the on-resistance of the clamp.
Journal ArticleDOI
MOSFET ESD Breakdown Modeling and Parameter Extraction in Advanced CMOS Technologies
TL;DR: In this paper, an approach for modeling the breakdown and snapback behavior of state-of-the-art MOSFET structures using equivalent-circuit description is described. But this approach is limited to the case where the junction and gate leakage currents due to the increased tunneling generation in the scaled-down CMOS.
Proceedings ArticleDOI
Channel Hot-Carrier degradation under static stress in short channel transistors with high-k/metal gate stacks
Esteve Amat,Thomas Kauerauf,Robin Degraeve,A. De Keersgieter,R. Rodriguez,Montserrat Nafria,X. Aymerich,Guido Groeseneken +7 more
TL;DR: In this paper, the authors analyzed the channel hot-carrier degradation in short channel transistors with a high-k gate stack processed in CMOS technology and found that the most damaging stress condition was VG = VD instead of the "classical" VG =VD/2 for long channel Transistors.