Learn the basic properties and designs of modern VLSI devices, as well as the factors affecting performance, with this thoroughly updated second edition. The first edition has been widely adopted as a standard textbook in microelectronics in many major US universities and worldwide. The internationally-renowned authors highlight the intricate interdependencies and subtle tradeoffs between various practically important device parameters, and also provide an in-depth discussion of device scaling and scaling limits of CMOS and bipolar devices. Equations and parameters provided are checked continuously against the reality of silicon data, making the book equally useful in practical transistor design and in the classroom. Every chapter has been updated to include the latest developments, such as MOSFET scale length theory, high-field transport model, and SiGe-base bipolar devices.

/pdf/fundamentals-of-modern-vlsi-devices-471xd7l9pf.pdf

Fundamentals of Modern VLSI Devices

Rise of silicene: A competitive 2D material

This paper focuses on approaches to continuing CMOS scaling by introducing new device structures and new materials. Starting from an analysis of the sources of improvements in device performance, we present technology options for achieving these performance enhancements. These options include high-dielectric-constant (high-k) gate dielectric, metal gate electrode, double-gate FET, and strained-silicon FET. Nanotechnology is examined in the context of continuing the progress in electronic systems enabled by silicon microelectronics technology. The carbon nanotube field-effect transistor is examined as an example of the evaluation process required to identify suitable nanotechnologies for such purposes.

Beyond the conventional transistor

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

To a large extent, scaling was not seriously challenged in the past. However, a closer look reveals that early signs of scaling limits were seen in high-performance devices in recent technology nodes. To obtain the projected performance gain of 30% per generation, device designers have been forced to relax the device subthreshold leakage continuously from one to several nA/µm for the 250-nm node to hundreds of nA/µm for the 65-nm node. Consequently, passive power density is now a significant portion of the power budget of a high-speed microprocessor. In this paper we discuss device and material options to improve device performance when conventional scaling is power-constrained. These options can be separated into three categories: improved short-channel behavior, improved current drive, and improved switching behavior. In the first category fall advanced dielectrics and multi-gate devices. The second category comprises mobility-enhancing measures through stress and substrate material alternatives. The third category focuses mainly on scaling of SOI body thickness to reduce capacitance. We do not provide details of the fabrication of these different device options or the manufacturing challenges that must be met. Rather, we discuss the fundamental scaling issues related to the various device options. We conclude with a brief discussion of the ultimate FET close to the fundamental silicon device limit.

Silicon CMOS devices beyond scaling

We review the basics of the extremely thin SOI (ETSOI) technology and how it addresses the main challenges of the CMOS scaling at the 20-nm technology node and beyond. The possibility of V T tuning with backbias, while keeping the channel undoped, opens up new opportunities that are unique to ETSOI. The main device characteristics with regard to low-power and high-performance logic, SRAM, analog and passive devices, and embedded memory are reviewed.

Extremely thin SOI for system-on-chip applications

A thin SOI ground plane (GP) design is explored for CMOS application beyond 65nm generation node The ground plane design is implemented using dopant implants at zero degree angle, in contrast to conventional halo implants, which are typically done at large implant angles The large angle implants may become impracticable as neighboring devices are positioned closer to each other in an ultra-scaled CMOS technology An intrinsic Si channel layer is epitaxially grown on top of the ground plane layer for improved surface layer transport The high doping ground plane layer is positioned away from the top interface, minimizing the counter-doping effect in the extension region, resulting in reduced extension resistance We demonstrate that the GP structure is effective in achieving superior DIBL and subthreshold slope characteristics down to Leff of ~35nm We also show that junction penalties in thin body SOI ground plane devices are within the acceptable range We demonstrate high speed ground plane CMOS ring oscillators, a stage delay of ~47ps is achieved at Vdd of 09V and 1muA/mum standby leakage current

Selective epitaxial channel ground plane thin SOI CMOS devices

In this work, we present very high performance CMOS devices with 50 nm channel lengths on 1.7 nm gate oxide, suitable for low temperature operation. Saturation transconductances of 1380 mS/mm for nMOSFETs and 523 mS/mm for pMOSFETs are achieved at -200 /spl deg/C. At the same temperature, I/sub on/ for a 1.2 V supply is 1.2 mA//spl mu/m for nMOSFET, and 0.5 mA//spl mu/m for pMOSFET, respectively, with I/sub off/ of both devices on the order of 10 nA//spl mu/m. A delay of 6.4 ps per stage at 1.5 V is measured at -100 /spl deg/C for a 101-stage CMOS ring oscillator. The delay of the same ring oscillator at room temperature is 8.2 ps per stage. These represent the highest CMOS performance figures reported to date.

Very high performance 50 nm CMOS at low temperature

In this paper, we present results and discuss issues related to implementation of large scale circuits in extremely thin (ET) SOI CMOS for low power applications. We have demonstrated that we can fabricate low power (LP) CMOS with centered Vts and good Vt uniformity across wafer and wafer to wafer. Using this CMOS, we have fabricated low leakage and high performance ring oscillators (with delay ∼20% faster than the standard 28 nm LP bulk). We have also obtained perfect 2.25M SRAM arrays, functioning down to Vdd of 0.5V, and we have shown that a 10-level BEOL process has minimal impact on device stability.

Assessment of fully-depleted planar CMOS for low power complex circuit operation

A radio frequency fully depleted silicon on insulator (RF-FDSOI) device and method of fabrication are provided. A silicon wafer for digital circuits is constructed using fully depleted silicon on insulator technology having a thin buried oxide layer. Localized areas of the silicon wafer are constructed for radio frequency circuits and/or passive devices. The silicon wafer has a silicon substrate having a resistivity greater than 1 KΩ·cm. The localized areas of the silicon wafer may include a trap rich layer implanted underneath a thin buried oxide layer. The localized areas of the silicon wafer may include a buried oxide layer that is thicker than the thin buried oxide layer. The thicker oxide layer is between 20 and 2000 nm thick. The localized areas of the silicon wafer may include a trap rich layer implanted underneath the thicker buried oxide layer.

J. Cai

Papers

Extremely thin SOI for system-on-chip applications

Selective epitaxial channel ground plane thin SOI CMOS devices

Very high performance 50 nm CMOS at low temperature

Assessment of fully-depleted planar CMOS for low power complex circuit operation

System on chip fully-depleted silicon on insulator with rf and mm-wave integrated functions