John Wallberg

TL;DR: The first all-digital PLL and polar transmitter for mobile phones is presented, exploiting the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom.

TL;DR: In this paper, the authors present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process, which is compatible with digital deep-submicron CMOS processes and can be readily integrated with a digital baseband and application processor.

TL;DR: A 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver.

TL;DR: A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time.

TL;DR: A discrete-time receiver architecture for a wireless application is presented and analog signal processing concepts are used to directly sample the RF input at Nyquist rate.