J
John Wallberg
Researcher at Texas Instruments
Publications - 36
Citations - 3070
John Wallberg is an academic researcher from Texas Instruments. The author has contributed to research in topics: Phase-locked loop & CMOS. The author has an hindex of 22, co-authored 36 publications receiving 2999 citations.
Papers
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Journal ArticleDOI
All-digital PLL and transmitter for mobile phones
Robert Bogdan Staszewski,John Wallberg,Sameh S. Rezeq,Chih-Ming Hung,Oren Eliezer,Sudheer Vemulapalli,C. Fernando,Kenneth J. Maggio,Robert B. Staszewski,N. Barton,Meng-Chang Lee,P. Cruise,Manouchehr Entezari,Khurram Muhammad,Dirk Leipold +14 more
TL;DR: The first all-digital PLL and polar transmitter for mobile phones is presented, exploiting the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom.
Journal ArticleDOI
All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS
Robert Bogdan Staszewski,Khurram Muhammad,Dirk Leipold,Chih-Ming Hung,Yo-Chuol Ho,John Wallberg,C. Fernando,Ken Maggio,Roman Staszewski,T. Jung,Jinseok Koh,S. John,I. Deng,Vivek Sarda,O. Moreira-Tamayo,Valerian Mayega,Ran Katz,Ofer Friedman,Oren Eliezer,Elida de-Obaldia,Poras T. Balsara +20 more
TL;DR: In this paper, the authors present a single-chip fully compliant Bluetooth radio fabricated in a digital 130-nm CMOS process, which is compatible with digital deep-submicron CMOS processes and can be readily integrated with a digital baseband and application processor.
Journal ArticleDOI
1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS
TL;DR: A 20-ps time-to-digital converter (TDC) realized in 90-nm digital CMOS is used as a phase/frequency detector and charge pump replacement in an all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications (GSM) transceiver.
Proceedings ArticleDOI
All-digital PLL and GSM/EDGE transmitter in 90nm CMOS
Robert Bogdan Staszewski,John Wallberg,Sameh S. Rezeq,Chih-Ming Hung,Oren Eliezer,Sudheer Vemulapalli,C. Fernando,Kenneth J. Maggio,Robert B. Staszewski,N. Barton,Meng-Chang Lee,P. Cruise,Manouchehr Entezari,Khurram Muhammad,Dirk Leipold +14 more
TL;DR: A 1.2V 42mA all-digital PLL and polar transmitter for a single-chip GSM/EDGE transceiver is implemented in 90nm CMOS and achieves -165dBc/Hz phase noise at 20MHz offset, with 10 /spl mu/s settling time.
Proceedings ArticleDOI
A discrete-time Bluetooth receiver in a 0.13/spl mu/m digital CMOS process
Khurram Muhammad,Dirk Leipold,Bogdan Staszewski,Yo-Chuol Ho,Chih-Ming Hung,Kenneth J. Maggio,C. Fernando,T. Jung,John Wallberg,Jinseok Koh,S. John,I. Deng,O. Moreira,Robert Bogdan Staszewski,Ran Katz,Ofer Friedman +15 more
TL;DR: A discrete-time receiver architecture for a wireless application is presented and analog signal processing concepts are used to directly sample the RF input at Nyquist rate.