C
Claire Fenouillet-Beranger
Researcher at University of Grenoble
Publications - 99
Citations - 2635
Claire Fenouillet-Beranger is an academic researcher from University of Grenoble. The author has contributed to research in topics: MOSFET & Silicon on insulator. The author has an hindex of 23, co-authored 98 publications receiving 2407 citations. Previous affiliations of Claire Fenouillet-Beranger include French Alternative Energies and Atomic Energy Commission & Commissariat à l'énergie atomique et aux énergies alternatives.
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Proceedings ArticleDOI
28nm FDSOI technology platform for high-speed low-voltage digital applications
Nicolas Planes,Olivier Weber,V. Barral,Sebastien Haendler,D. Noblet,D. Croain,M. Bocat,P.O. Sassoulas,Xavier Federspiel,Antoine Cros,A. Bajolet,E. Richard,B. Dumont,Pierre Perreau,David Petit,Dominique Golanski,Claire Fenouillet-Beranger,N. Guillot,Mustapha Rafik,Vincent Huard,S. Puget,X. Montagner,M-A. Jaud,O. Rozeau,O. Saxod,Francois Wacquant,Frederic Monsieur,D. Barge,L. Pinzelli,M. Mellier,Frederic Boeuf,Franck Arnaud,Michel Haond +32 more
TL;DR: This work demonstrates 32% and 84% speed boost at 1.0V and 0.6V respectively, without adding process complexity compared to standard bulk technology, to show how memory access time can be significantly reduced thanks to high Iread, by keeping competitive leakage values.
Journal ArticleDOI
Plasma wave detection of terahertz radiation by silicon field effects transistors: Responsivity and noise equivalent power
R. Tauk,Frederic Teppe,S. Boubanga,D. Coquillat,Wojciech Knap,Yahya Moubarak Meziani,C. Gallon,Frederic Boeuf,Thomas Skotnicki,Claire Fenouillet-Beranger,Duncan K. Maude,Sergey L. Rumyantsev,Michael Shur +12 more
TL;DR: In this paper, Si metal oxide semiconductor field effect transistors (MOSFETs) with the gate lengths of 120-300nm have been studied as room temperature plasma wave detectors of 0.7THz electromagnetic radiation.
Journal ArticleDOI
Innovative Materials, Devices, and CMOS Technologies for Low-Power Mobile Multimedia
Thomas Skotnicki,Claire Fenouillet-Beranger,C. Gallon,F. Buf,Stephane Monfray,F. Payet,A. Pouydebasque,M. Szczap,Alexis Farcy,Franck Arnaud,Sylvain Clerc,M. Sellier,A. Cathignol,Jean-Pierre Schoellkopf,E. Perea,R. Ferrant,H. Mingam +16 more
TL;DR: In this article, a detailed analysis and potential solutions for prolonging CMOS as the leading information technology are presented, along with the state of the art, requirements, and solutions at the level of materials, transistor, and technology.
Proceedings ArticleDOI
High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding
Olivier Weber,O. Faynot,Francois Andrieu,C. Buj-Dufournet,F. Allain,P. Scheiblin,J. Foucher,Nicolas Daval,D. Lafond,L. Tosti,L. Brevard,Olivier Rozeau,Claire Fenouillet-Beranger,M. Marin,Frederic Boeuf,Daniel Delprat,Konstantin Bourdelle,Bich-Yen Nguyen,Simon Deleonibus +18 more
TL;DR: In this paper, the authors investigated the sources responsible for local and inter-die threshold voltage variability in undoped ultra-thin FDSOI MOSFETs with a high-k/metal gate stack.
Proceedings ArticleDOI
Planar Fully depleted SOI technology: A powerful architecture for the 20nm node and beyond
O. Faynot,Francois Andrieu,Olivier Weber,Claire Fenouillet-Beranger,Pierre Perreau,J. Mazurier,T. Benoist,O. Rozeau,Thierry Poiroux,Maud Vinet,Laurent Grenouillet,J.-P. Noel,Nicolas Posseme,Sébastien Barnola,François Martin,C. Lapeyre,Mikael Casse,X. Garros,M-A. Jaud,Olivier P. Thomas,G. Cibrario,L. Tosti,L. Brevard,Claude Tabone,P. Gaud,Sylvain Barraud,Thomas Ernst,Simon Deleonibus +27 more
TL;DR: In this article, the main advantages of planar undoped channel Fully depleted SOI devices are discussed and solutions to the Multiple V T challenges and non logic devices (ESD, I/Os) are reported.