L
Laurent Brunet
Researcher at University of Grenoble
Publications - 68
Citations - 818
Laurent Brunet is an academic researcher from University of Grenoble. The author has contributed to research in topics: Transistor & NMOS logic. The author has an hindex of 13, co-authored 62 publications receiving 608 citations. Previous affiliations of Laurent Brunet include European Automobile Manufacturers Association.
Papers
More filters
Proceedings ArticleDOI
3DVLSI with CoolCube process: An alternative path to scaling
Perrine Batude,Claire Fenouillet-Beranger,L. Pasini,V. Lu,F. Deprat,Laurent Brunet,Benoit Sklenard,F. Piegas-Luce,M. Casse,B. Mathieu,O. Billoint,G. Cibrario,Ogun Turkyilmaz,Hossam Sarhan,Sebastien Thuries,Louis Hutin,S. Sollier,Julie Widiez,L. Hortemel,Claude Tabone,M.-P. Samson,Bernard Previtali,N. Rambal,F. Ponthenier,J. Mazurier,Remi Beneyton,M. Bidaud,Emmanuel Josse,E. Petitprez,O. Rozeau,Maurice Rivoire,C. Euvard-Colnat,A. Seignard,F. Fournel,L. Benaissa,Perceval Coudrain,P. Leduc,J.M. Hartmann,Pascal Besson,Sebastien Kerdiles,C. Bout,Fabrice Nemouchi,A. Royer,C. Agraffeil,G. Ghibaudo,Thomas Signamarcheix,Michel Haond,Fabien Clermidy,O. Faynot,Maud Vinet +49 more
TL;DR: In this paper, the authors propose a 3D VLSI with a CoolCube integration to vertically stack several layers of devices with a unique connecting via density above a million/mm2.
Proceedings ArticleDOI
3D Sequential Integration: Application-driven technological achievements and guidelines
Perrine Batude,Laurent Brunet,C. Fenouillet-Beranger,Francois Andrieu,J.-P. Colinge,Didier Lattard,E. Vianello,Sebastien Thuries,O. Billoint,Pascal Vivet,Cristiano Santos,B. Mathieu,Benoit Sklenard,C.-M. V. Lu,J. Micout,F. Deprat,E. Avelar Mercado,F. Ponthenier,N. Rambal,M.-P. Samson,M. Casse,Sebastien Hentz,Julien Arcamone,Gilles Sicard,Louis Hutin,L. Pasini,A. Ayres,O. Rozeau,R. Berthelon,Fabrice Nemouchi,Philippe Rodriguez,J.-B. Pin,D. Larmagnac,A. Duboust,V. Ripoche,S. Barraud,N. Allouti,Sébastien Barnola,C. Vizioz,J.M. Hartmann,Sebastien Kerdiles,P. Acosta Alba,S. Beaurepaire,V. Beugin,F. Fournel,Pascal Besson,Virginie Loup,R. Gassilloud,François Martin,X. Garros,Frédéric Mazen,Bernard Previtali,C. Euvrard-Colnat,V. Balan,C. Comboroure,M. Zussy,Mazzocchi,O. Faynot,M. Vinet +58 more
TL;DR: 3D Sequential Integration with ultra-small 3D contact pitch with Ultra-Low TB FETs has potential for low-power applications and allow for the stacking of multiple layers.
Proceedings ArticleDOI
First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers
Laurent Brunet,Perrine Batude,Claire Fenouillet-Beranger,P. Besombes,L. Hortemel,F. Ponthenier,Bernard Previtali,Claude Tabone,A. Royer,C. Agraffeil,C. Euvrard-Colnat,A. Seignard,Christophe Morales,F. Fournel,L. Benaissa,Thomas Signamarcheix,Pascal Besson,M. Jourdan,R. Kachtouli,V. Benevent,J.M. Hartmann,C. Comboroure,N. Allouti,Nicolas Posseme,C. Vizioz,Christian Arvet,Sébastien Barnola,Sebastien Kerdiles,L. Baud,L. Pasini,C.-M. V. Lu,F. Deprat,Alain Toffoli,G. Romano,C. Guedj,Vincent Delaye,Frederic Boeuf,O. Faynot,Maud Vinet +38 more
TL;DR: In this article, a full 3D CMOS over CMOS CoolCube integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain.
Proceedings ArticleDOI
3D sequential integration opportunities and technology optimization
Perrine Batude,Benoit Sklenard,Claire Fenouillet-Beranger,Bernard Previtali,Claude Tabone,Olivier Rozeau,O. Billoint,Ogun Turkyilmaz,Hossam Sarhan,Sebastien Thuries,G. Cibrario,Laurent Brunet,F. Deprat,J-E. Michallet,Fabien Clermidy,M. Vinet +15 more
TL;DR: In this article, a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity is presented. And the authors summarize the technological challenges of this concept.
Proceedings ArticleDOI
New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI
Claire Fenouillet-Beranger,B. Mathieu,Bernard Previtali,M.-P. Samson,N. Rambal,V. Benevent,Sebastien Kerdiles,J.P. Barnes,D. Barge,Pascal Besson,R. Kachtouli,M. Casse,X. Garros,A. Laurent,Fabrice Nemouchi,Karim Huet,I. Toque-Tresonne,D. Lafond,H. Dansas,F. Aussenac,G. Druais,Pierre Perreau,E. Richard,S. Chhun,E. Petitprez,N. Guillot,F. Deprat,L. Pasini,Laurent Brunet,V. Lu,C. Reita,Perrine Batude,M. Vinet +32 more
TL;DR: In this article, the maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure transistors stability in sequential 3D integration.