There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

As a fascinating conjugated polymer, graphitic carbon nitride (g-C3N4) has become a new research hotspot and drawn broad interdisciplinary attention as a metal-free and visible-light-responsive photocatalyst in the arena of solar energy conversion and environmental remediation. This is due to its appealing electronic band structure, high physicochemical stability, and “earth-abundant” nature. This critical review summarizes a panorama of the latest progress related to the design and construction of pristine g-C3N4 and g-C3N4-based nanocomposites, including (1) nanoarchitecture design of bare g-C3N4, such as hard and soft templating approaches, supramolecular preorganization assembly, exfoliation, and template-free synthesis routes, (2) functionalization of g-C3N4 at an atomic level (elemental doping) and molecular level (copolymerization), and (3) modification of g-C3N4 with well-matched energy levels of another semiconductor or a metal as a cocatalyst to form heterojunction nanostructures. The constructi...

Graphitic Carbon Nitride (g-C3N4)-Based Photocatalysts for Artificial Photosynthesis and Environmental Remediation: Are We a Step Closer To Achieving Sustainability?

Many metal–insulator–metal systems show electrically induced resistive switching effects and have therefore been proposed as the basis for future non-volatile memories. They combine the advantages of Flash and DRAM (dynamic random access memories) while avoiding their drawbacks, and they might be highly scalable. Here we propose a coarse-grained classification into primarily thermal, electrical or ion-migration-induced switching mechanisms. The ion-migration effects are coupled to redox processes which cause the change in resistance. They are subdivided into cation-migration cells, based on the electrochemical growth and dissolution of metallic filaments, and anion-migration cells, typically realized with transition metal oxides as the insulator, in which electronically conducting paths of sub-oxides are formed and removed by local redox processes. From this insight, we take a brief look into molecular switching systems. Finally, we discuss chip architecture and scaling issues.

http://chialvo.org/Curso/UBACurso/DIA7/Papers/Aono_NatMat_07_Ionic%20Switching%20Memory.pdf

Nanoionics-based resistive switching memories

Redox‐Based Resistive Switching Memories – Nanoionic Mechanisms, Prospects, and Challenges

A memristor is a two-terminal electronic device whose conductance can be precisely modulated by charge or flux through it. Here we experimentally demonstrate a nanoscale silicon-based memristor device and show that a hybrid system composed of complementary metal−oxide semiconductor neurons and memristor synapses can support important synaptic functions such as spike timing dependent plasticity. Using memristors as synapses in neuromorphic circuits can potentially offer both high connectivity and high density required for efficient computing.

/pdf/nanoscale-memristor-device-as-synapse-in-neuromorphic-1sl2njhdyu.pdf

Nanoscale Memristor Device as Synapse in Neuromorphic Systems

For the first time, an energy-efficient hybrid precoding with computing-in-memory technology for 5G/6G MIMO communication system is demonstrated. To meet the requirement of massive matrix multiplication for MIMO signal processing, we realize the first fully-parallel large-scale (128K) analog resistive switching RRAM array. In order to address the IR-drop issue caused by both interconnect resistance and peripheral circuit in the fully-parallel large-scale arrays, a compact model and corresponding compensation scheme are proposed. To address the computation complexity challenge of hybrid precoding, we design a new CIM-compatible analog precoding scheme and mapping strategy. The demonstrated CIM-based hybrid precoding system achieves FPGA-comparable sum rates (13.17 bps/Hz @ 0dB SNR) and 20.2 × higher energy efficiency than FPGA. This work explores the feasibility of in-MIMO hybrid precoding with analog RRAM for future 5G/6G high-speed communication systems.

Hybrid Precoding with a Fully-Parallel Large-Scale Analog RRAM Array for 5G/6G MIMO Communication System

The present invention discloses a preparation method of a Cu-based resistive random access memory, and a memory. The preparation method includes: performing composition and a chemical combination treatment on a lower copper electrode (10) to generate a compound buffer layer (40), wherein the compound buffer layer (40) is capable of preventing the oxidation of the lower copper electrode (10); depositing a solid electrolyte material (50) on the compound buffer layer (40); and depositing an upper electrode (60) on the solid electrolyte material (50) to form the memory. In the above technical solution, the compound buffer layer (40) capable of preventing the oxidation of the lower copper electrode (10) is inserted between the lower copper electrode (10) and the solid electrolyte material (50) to efficiently prevent the oxidation of the lower copper electrode (10) in a growth process of the solid electrolyte material (50), such that an electrode interface does not become rough due to the oxidation, thereby solving the technical problem of relatively low reliability and yield of the device resulting from the rough electrode interface of the Cu-based resistive random access memory in the prior art, and thus the reliability and the yield of the device are improved.

Preparation method of Cu-based resistive random access memory, and memory

Disclosed a three-terminal atom switch device and a manufacturing method therefor The three-terminal atom switch device comprises a stacking structure comprising a source end (301) and a drain end (302), a vertical groove formed by etching the stacking structure, an M8XY6 channel layer (501) formed on the inner wall and the bottom of the vertical groove, and a control end (601) formed on the surface of the M8XY6 channel layer (501) The vertical groove is full of the control end (601) A source end resistor and a drain end resistor are regulated by the control end On the basis of the three-terminal atom switch device, the high switching ratio feature is achieved in the height nonlinear change characteristic of the resistance between the source end and the drain end along with the voltage of the control end; the structure is simple, the integration is easy, the density is high, the cost is low, the three-terminal atom switch device can be used in a gating tube of a cross array structure, and the crosstalk phenomenon caused by leaked current is restrained The three-terminal atom switch device is also suitable for a plane stacking cross array structure and a vertical cross array structure, and the high-density three-dimensional storage is achieved

Three-terminal atom switch device and manufacturing method therefor

This work presents a 14-bit 500 MS/s single-channel pipelined-successive-approximation-register (SAR) analog-to-digital converter (ADC) with an adaptively biased floating inverter amplifier (AB-FIA) as the residue amplifier (RA) and a hybrid reference ripple mitigation (H-RRM) technique to relax the power and area burden on the reference stabilization. Leveraging the adaptively biased architecture in the last stage FIA, the speed and open-loop gain of the proposed two-stage FIA are enhanced compared with the conventional cascode counterpart. Besides, the impact of the reference error on the pipelined-SAR conversion accuracy is alleviated by hybridizing the improved reference ripple cancellation (RRC), reference ripple neutralization (RRN), and reference buffer (RBUF). The improved RRC removes the potential noise coupled from the floating capacitor to counter the decision error during the sub-SAR conversion in the first stage. Meanwhile, the RRN facilitates a rapid reference recovery. These acts constitute the H-RRM, which assists a high-speed and high-resolution pipelined-SAR process with a relaxed integrated reference RBUF with low-power and compact area. The prototype ADC was fabricated in a 28 nm CMOS process; it consumes 6.34 mW total power at 500 MS/s, including 2.4 mW dynamic power of RBUF. It occupies an active area of 0.018 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> , which the ADC core area of 0.0168 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and the area of RBUF with a 2.3 pF decoupling capacitor is 0.00105 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> . The measured signal to noise and distortion ratio (SNDR) and spurious free dynamic range (SFDR) are 64.2 dB and 80.55 dB with a Nyquist input, respectively, leading to a 170.2 dB Schreier figure-of-merit (FoM) (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{S}}$</tex-math> </inline-formula> ) and 9.6 fJ/conversion-step Walden FoM (FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{\mathrm{W}}$</tex-math> </inline-formula> ). 

Qi Liu

Papers

Hybrid Precoding with a Fully-Parallel Large-Scale Analog RRAM Array for 5G/6G MIMO Communication System

Preparation method of Cu-based resistive random access memory, and memory

Three-terminal atom switch device and manufacturing method therefor

A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier