Runsheng Wang

TL;DR: In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and the impact of process variation are investigated for the first time, and the results indicate that SNWTs exhibit superior intrinsic RF scaling capability and are suitable for low-power analog and RF applications.

TL;DR: In this article, the impacts of interface traps on tunneling FET (TFET) are examined in terms of different trap energies and distributions, charge neutrality level (CNL), and effects of random trap fluctuation, in comparison with MOSFET.

TL;DR: In this article, low-frequency noise (LFN) in n-type silicon nanowire MOSFETs is investigated and the measured results show that LFN in SNWTs can be well described by the correlated-mobility fluctuation model at low drain current, with the effective oxide trap density extracted and discussed.

TL;DR: In this article, experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach.

TL;DR: It is shown that the transport properties of BP device under high electric field can be improved greatly by the interface engineering of high-quality HfLaO dielectrics and transport orientation and by designing the device channels along the lower effective mass armchair direction.