S
Srinivas Devadas
Researcher at Massachusetts Institute of Technology
Publications - 498
Citations - 35003
Srinivas Devadas is an academic researcher from Massachusetts Institute of Technology. The author has contributed to research in topics: Sequential logic & Combinational logic. The author has an hindex of 88, co-authored 480 publications receiving 31897 citations. Previous affiliations of Srinivas Devadas include University of California, Berkeley & Cornell University.
Papers
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Proceedings ArticleDOI
Physical unclonable functions for device authentication and secret key generation
G. Edward Suh,Srinivas Devadas +1 more
TL;DR: This work presents PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describes how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.
Proceedings ArticleDOI
Silicon physical random functions
TL;DR: It is argued that a complex integrated circuit can be viewed as a silicon PUF and a technique to identify and authenticate individual integrated circuits (ICs) is described.
Journal ArticleDOI
Extracting secret keys from integrated circuits
TL;DR: It is shown that arbiter-based PUFs are realizable and well suited to build key-cards that need to be resistant to physical attacks and to be identified securely and reliably over a practical range of environmental variations such as temperature and power supply voltage.
Journal ArticleDOI
Physical Unclonable Functions and Applications: A Tutorial
TL;DR: This paper motivates the use of PUFs versus conventional secure nonvolatile memories, defines the two primary PUF types, and describes strong and weak PUF implementations and their use for low-cost authentication and key generation applications.
Proceedings ArticleDOI
A technique to build a secret key in integrated circuits for identification and authentication applications
TL;DR: It is shown that there exists enough delay variation across ICs implementing, the proposed circuit to identify individual ICs, to build a secret key unique to each IC.