Today’s smartphone operating systems frequently fail to provide users with visibility into how third-party applications collect and share their private data. We address these shortcomings with TaintDroid, an efficient, system-wide dynamic taint tracking and analysis system capable of simultaneously tracking multiple sources of sensitive data. TaintDroid enables realtime analysis by leveraging Android’s virtualized execution environment. TaintDroid incurs only 32p performance overhead on a CPU-bound microbenchmark and imposes negligible overhead on interactive third-party applications. Using TaintDroid to monitor the behavior of 30 popular third-party Android applications, in our 2010 study we found 20 applications potentially misused users’ private information; so did a similar fraction of the tested applications in our 2012 study. Monitoring the flow of privacy-sensitive data with TaintDroid provides valuable input for smartphone users and security service firms seeking to identify misbehaving applications.

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TaintDroid: An Information-Flow Tracking System for Realtime Privacy Monitoring on Smartphones

Today's smartphone operating systems frequently fail to provide users with adequate control over and visibility into how third-party applications use their private data. We address these shortcomings with TaintDroid, an efficient, system-wide dynamic taint tracking and analysis system capable of simultaneously tracking multiple sources of sensitive data. TaintDroid provides realtime analysis by leveraging Android's virtualized execution environment. TaintDroid incurs only 14% performance overhead on a CPU-bound micro-benchmark and imposes negligible overhead on interactive third-party applications. Using TaintDroid to monitor the behavior of 30 popular third-party Android applications, we found 68 instances of potential misuse of users' private information across 20 applications. Monitoring sensitive data with TaintDroid provides informed use of third-party applications for phone users and valuable input for smartphone security service firms seeking to identify misbehaving applications.

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TaintDroid: an information-flow tracking system for realtime privacy monitoring on smartphones

Ordered Binary-Decision Diagrams (OBDDs) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satisfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD data structures. Using OBDDs, a wide variety of problems can be solved through symbolic analysis. First, the possible variations in system parameters and operating conditions are encoded with Boolean variables. Then the system is evaluated for all variations by a sequence of OBDD operations. Researchers have thus solved a number of problems in digital-system design, finite-state system analysis, artificial intelligence, and mathematical logic. This paper describes the OBDD data structure and surveys a number of applications that have been solved by OBDD-based symbolic analysis.

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Symbolic Boolean manipulation with ordered binary-decision diagrams

Physical Unclonable Functions (PUFs) are innovative circuit primitives that extract secrets from physical characteristics of integrated circuits (ICs). We present PUF designs that exploit inherent delay characteristics of wires and transistors that differ from chip to chip, and describe how PUFs can enable low-cost authentication of individual ICs and generate volatile secret keys for cryptographic operations.

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Physical unclonable functions for device authentication and secret key generation

Physical Unclonable Functions for Device Authentication and Secret Key Generation

Chip-multiprocessors (CMPs) have become the mainstream chip design in recent years; for scalability reasons, designs with high core counts tend towards tiled CMPs with physically distributed shared caches. This naturally leads to a Non-Uniform Cache Architecture (NUCA) design, where onchip access latencies depend on the physical distances between requesting cores and home cores where the data is cached. Improving data locality is thus key to performance, and several studies have addressed this problem using data replication and data migration. In this paper, we consider another mechanism, hardwarelevel thread migration. This approach, we argue, can better exploit shared data locality for NUCA designs by effectively replacing multiple round-trip remote cache accesses with a smaller number of migrations. High migration costs, however, make it crucial to use thread migrations judiciously; we therefore propose a novel, on-line prediction scheme which decides whether to perform a remote access (as in traditional NUCA designs) or to perform a thread migration at the instruction level. For a set of parallel benchmarks, our thread migration predictor improves the performance by 18% on average and at best by 2.3X over the standard NUCA design that only uses remote accesses.

Judicious Thread Migration When Accessing Distributed Shared Caches

Wepresent the Instruction Set Description Language, ISDL, a machinedescription language used to describe target architectures toa set of retargetable design tools including compilers and simulators.Such tools enable the design of embedded system processors bysupporting the exploration of the architecture design space.The features and flexibility of ISDL enable the description ofa wide variety of architectures with emphasis on VLIW architectures.ISDL explicitly supports constraints that define valid operationgroupings within an instruction, thus increasing the range ofspecifiable architectures and resulting in concise and intuitivedescriptions. Furthermore, a single ISDL description supportsthe automatic generation or retargeting of all of the designevaluation tools. This paper presents the structure and featuresof ISDL and describes how the information in an ISDL descriptionmay be used to retarget or generate assemblers, disassemblers,compilers, simulators, and hardware models. In addition, it comparesISDL to various other machine description languages that arebeing used for embedded processor design. Various complicationsthat arose while describing real-world architectures (which includea powerful seven-way VLIW processor and the Motorola 56000 DSP)and the solutions to these complications are also presented.

ISDL: An Instruction Set Description Language for Retargetability and Architecture Exploration

Directory-based cache coherence is a popular mechanism for chip multiprocessors and multicores. The directory protocol, however, requires multicast for invalidation messages and the collection of acknowledgement messages, which can be expensive in terms of latency and network traffic. Furthermore, the size of the directory increases with the number of cores. We present Library Cache Coherence (LCC), which requires neither broadcast/multicast for invalidations nor waiting for invalidation acknowledgements. A library is a set of timestamps that are used to auto-invalidate shared cache lines, and delay writes on the lines until all shared copies expire. The size of library is independent of the number of cores. By removing the complex invalidation process of directorybased cache coherence protocols, LCC generates fewer network messages. At the same time, LCC also allows reads on a cache block to take place while a write to the block is being delayed, without breaking sequential consistency. As a result, LCC has 1.85X less average memory latency than a MESI directory-based protocol on our set of benchmarks, even with a simple timestamp choosing algorithm; moreover, our experimental results on LCC with an ideal timestamp scheme (though not implementable) show the potential of further improvement for LCC with more sophisticated timestamp schemes.

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Library Cache Coherence

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Taurus: lightweight parallel logging for in-memory database management systems

A minimization procedure of prime-implicant generation and covering that operates on symbolic outputs rather than binary-valued outputs is proposed for solving the output encoding problem. An exact solution to this minimization problem is also an exact solution to the encoding problem. While this covering problem is more complex than the classic unate covering problem, a single O(N factorial) logic minimization step replaces O(N factorial) minimizations. An exact algorithm is presented for state assignment by generalizing the output encoding approach to the multiple-valued input case. Preliminary experimental results are presented which indicate that medium-sized problems can be solved exactly. Computationally efficient heuristic approaches based on the exact algorithms are proposed for output encoding, state assignment, and four-level Boolean minimization. >

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Srinivas Devadas

Papers

Judicious Thread Migration When Accessing Distributed Shared Caches

ISDL: An Instruction Set Description Language for Retargetability and Architecture Exploration

Library Cache Coherence

Taurus: lightweight parallel logging for in-memory database management systems

Exact algorithms for output encoding, state assignment and four-level Boolean minimization