Srinivas Devadas

TL;DR: A new metric for measuring the extent of design verification provided by a set of functional simulation vectors is proposed, which can be used uniformly for all designs and computes observability information to determine whether effects of errors that are activated by the program stimuli can be observed at the circuit outputs.

TL;DR: This work proposes an efficient hardware indirect memory prefetcher (IMP) to capture this access pattern and hide latency, and proposes a partial cacheline accessing mechanism for these prefetches to reduce the network and DRAM bandwidth pressure from the lack of spatial locality.

TL;DR: A novel test procedure that exploits the structure of the combinational logic in the circuit as well as the sequential behavior of the circuit is presented and superior performance of this approach as compared to previous approaches to FSM verification is presented.

Abstract: Keeping user data private is a huge problem both in cloud computing and computation outsourcing. One paradigm to achieve data privacy is to use tamper-resistant processors, inside which users' private data is decrypted and computed upon. These processors need to interact with untrusted external memory. Even if we encrypt all data that leaves the trusted processor, however, the address sequence that goes off-chip may still leak information. To prevent this address leakage, the security community has proposed ORAM (Oblivious RAM). ORAM has mainly been explored in server/file settings which assume a vastly different computation model than secure processors. Not surprisingly, naively applying ORAM to a secure processor setting incurs large performance overheads.In this paper, a recent proposal called Path ORAM is studied. We demonstrate techniques to make Path ORAM practical in a secure processor setting. We introduce background eviction schemes to prevent Path ORAM failure and allow for a performance-driven design space exploration. We propose a concept called super blocks to further improve Path ORAM's performance, and also show an efficient integrity verification scheme for Path ORAM. With our optimizations, Path ORAM overhead drops by 41.8%, and SPEC benchmark execution time improves by 52.4% in relation to a baseline configuration. Our work can be used to improve the security level of previous secure processors.

TL;DR: This paper shows how one can implement a very large number of virtual monotonic counters on an untrusted machine with a Trusted Platform Module (TPM) or similar device, without relying on a trusted OS, and implements a hash-tree-based scheme that offers improved performance and scalability.