There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

/pdf/rediscovering-black-phosphorus-as-an-anisotropic-layered-40dpp6m2eu.pdf

Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

Algorithm choices and corresponding VLSI architectures for spatial multiplexing receivers in multiple-input multiple-output (MIMO) communication systems are described in this paper. Implementations of linear and successive interference cancellation receivers are compared to implementations of maximum likelihood (ML) decoders that attain optimum bit error rate performance. The presented designs provide reference for the true silicon complexity of the algorithms under consideration and help to identify the limits with respect to practical implementations.

Receiver design for multi-antenna wireless communications

A complete optical-electronical simulation of a GaAs based MSM photodetector is presented. In the modeling, rigorous electromagnetic methods for the light propagation have been combined with particle-based Monte-Carlo electronic device simulation methods.

Optical-electronic simulation of a GaAs metal-semiconductor-metal (MSM) photodetector

Over the past decade, the utilization of technology CAD (TCAD) tools has become widespread in industry and academia. The enormous progress in computing hardware and software technology, together with significant advances in physical modelling accuracy, and speed and robustness of numerical algorithms, have made TCAD to a cost-effective albeit powerful technology that complements experimental approaches to wafer processing and metrology.

https://ieeexplore.ieee.org/iel5/9957/32010/01487939.pdf

Progress in Technology CAD for Power Devices, Circuits and Systems

The thermal mixed-mode capabilities of the device and circuit simulator Dessis are presented. The mode allows both electrical and thermal netlists to interconnect physical and circuit devices. As an example, the full electrothermal simulation of IGBT power module is presented.

Large Scale Thermal Mixed Mode Device and Circuit Simulation

We present PARDISO, a new parallel sparse direct linear solver for large-scale parallel semiconductor device and process simulations on shared memory multiprocessors. Since robust transient 2-D and 3-D simulations necessitate large computing resources, the choice of architectures, algorithms and their implementations becomes of utmost importance. Sparse direct methods are the most robust methods over a wide range of numerical properties and therefore PARDISO has been integrated into complex semiconductor device and process simulation packages. We have investigated popular shared memory multiprocessors and the most popular numerical algorithms commonly used for the solution of the classical drift-diffusion and the diffusion-reaction equations in process simulation. The study includes a preconditioned iterative linear solver package and our parallel direct linear solver. Moreover, we have investigated the efficiency and the limits of our parallel approach. Results of several simulations of up to 100’000 vertices for three-dimensional device simulations are presented to illustrate our approach towards robust, parallel semiconductor device and process simulation.

Wolfgang Fichtner

Papers

Receiver design for multi-antenna wireless communications

Optical-electronic simulation of a GaAs metal-semiconductor-metal (MSM) photodetector

Progress in Technology CAD for Power Devices, Circuits and Systems

Large Scale Thermal Mixed Mode Device and Circuit Simulation

Numerical semiconductor device and process simulation on shared memory multiprocessors: algorithms, architectures results