There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

The problem of achieving compact, high-performance forced liquid cooling of planar integrated circuits has been investigated. The convective heat-transfer coefficient h between the substrate and the coolant was found to be the primary impediment to achieving low thermal resistance. For laminar flow in confined channels, h scales inversely with channel width, making microscopic channels desirable. The coolant viscosity determines the minimum practical channel width. The use of high-aspect ratio channels to increase surface area will, to an extent, further reduce thermal resistance. Based on these considerations, a new, very compact, water-cooled integral heat sink for silicon integrated circuits has been designed and tested. At a power density of 790 W/cm2, a maximum substrate temperature rise of 71°C above the input water temperature was measured, in good agreement with theory. By allowing such high power densities, the heat sink may greatly enhance the feasibility of ultrahigh-speed VLSI circuits.

High-performance heat sinking for VLSI

The applications of graphene and transition metal dichalcogenides in electronics are limited by their zero-bandgap and low mobility, respectively. Here, the authors demonstrate the potential of an emerging layered material—black phosphorous—for thin film electronics and infrared optoelectronics.

/pdf/rediscovering-black-phosphorus-as-an-anisotropic-layered-40dpp6m2eu.pdf

Rediscovering black phosphorus as an anisotropic layered material for optoelectronics and electronics

Power dissipation and thermal issues are increasingly significant in modern processors. As a result, it is crucial that power/performance tradeoffs be made more visible to chip architects and even compiler writers, in addition to circuit designers. Most existing power analysis tools achieve high accuracy by calculating power estimates for designs only after layout or floorplanning are complete. In addition to being available only late in the design process, such tools are often quite slow, which compounds the difficulty of running them for a large space of design possibilities.This paper presents Wattch, a framework for analyzing and optimizing microprocessor power dissipation at the architecture-level. Wattch is 1000X or more faster than existing layout-level power tools, and yet maintains accuracy within 10% of their estimates as verified using industry tools on leading-edge designs. This paper presents several validations of Wattch's accuracy. In addition, we present three examples that demonstrate how architects or compiler writers might use Wattch to evaluate power consumption in their design process.We see Wattch as a complement to existing lower-level tools; it allows architects to explore and cull the design space early on, using faster, higher-level tools. It also opens up the field of power-efficient computing to a wider range of researchers by providing a power evaluation methodology within the portable and familiar SimpleScalar framework.

Wattch: a framework for architectural-level power analysis and optimizations

National Institute of Standards and Technology における超伝導研究及び生活

The implementation of high voltage vertical bipolar transistors in a BiCMOS technology requires sufficient space for the extension of the collector-base depletion region. Assuming that layout design rules for high voltage devices are used, the open base breakdown voltage BVceo is only defined by the one-dimensional vertical doping profile through the n+-emitter, the p-base, the n-intrinsic and the n+-extrinsic collector, i.e. lateral effects can be neglected for this type of brakdown. This paper describes the derivation of simple equations for optimizing the n+pn−n+-structure. Closed-form analytical equations based on the impact ionization model from Fulop ([1] Solid St. Electron. 10, 39 (1967)) yield the dependence of the open base breakdown voltage BVceo on the transistor gain, doping level and width of the intrinsic collector.

Optimizing high voltage bipolar transistors in a smart-power complementary BiCMOS technology

In this presentation, a fully 3-dimensional laser simulator for quantum well laser diodes has been developed which is based on DESSIS/sub -ISE/. It utilizes a rate equation description for the coupling between optics and electronics. Capture and emission rates for the bound and free carriers are used for the quantum-well. The electronic and the optical equations are solved in a self-consistent manner.

A full 3-dimensional quantum well laser simulation

Beamforming (BF) for multiple-input multiple-output (MIMO) wireless communications systems can improve the error rate performance by spatial separation of the transmitted data streams. BF requires to feed back steering matrices from the receiver to the transmitter. The usually large amount of feedback data asks for data reduction schemes. In this paper, we investigate the error rate performance/feedback rate trade-off associated with steering matrix data-reduction schemes and present a corresponding hardware-optimized compression/decompression architecture. Our VLSI implementation achieves up to 50% data reduction for 4times4-dimensional steering matrices without a significant decrease in terms of error rate performance at a circuit complexity of only 7 k gate equivalents.

/pdf/vlsi-architecture-for-data-reduced-steering-matrix-feedback-m4kgommpz4.pdf

VLSI architecture for data-reduced steering matrix feedback in MIMO systems

Device Simulation and Backside Laser Interferometry––Powerful Tools for ESD Protection Development

Since general-purpose 3D process simulators are currently not available, solid modelers greatly help the designer in building geometries for device simulators. In this contribution, a solid modeler is presented that allows reliable geometrical operations. In order to avoid numerical errors occurring at the intersection of objects built with polygons, we have chosen a data structure based on a discretization of the x-y plane of the simulation domain. >

http://ieeexplore.ieee.org/iel2/1117/8015/00343493.pdf

Wolfgang Fichtner

Papers

Optimizing high voltage bipolar transistors in a smart-power complementary BiCMOS technology

A full 3-dimensional quantum well laser simulation

VLSI architecture for data-reduced steering matrix feedback in MIMO systems

Device Simulation and Backside Laser Interferometry––Powerful Tools for ESD Protection Development

Reliable solid modeling for three-dimensional semiconductor process and device simulation